[coreboot-gerrit] New patch to review for coreboot: bbdfdde t132: em100 helper

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10259

-gerrit

commit bbdfdde4b1aaa3fcbc7654675b2131d05533c1a1
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri May 15 13:24:24 2015 -0500

    t132: em100 helper
    
    Change-Id: I7c56c3f9a987be67dd3a0053c21ddceb68f13359
---
 src/mainboard/google/rush_ryu/bootblock.c | 4 ++--
 src/soc/nvidia/tegra132/spi.c             | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c
index 232baaf..dcb4444 100644
--- a/src/mainboard/google/rush_ryu/bootblock.c
+++ b/src/mainboard/google/rush_ryu/bootblock.c
@@ -59,8 +59,8 @@ static const struct pad_config spiflash_pads[] = {
 static const struct funit_cfg funits[] = {
 	/* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */
 	FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)),
-	/* SPI flash at 33MHz on SPI4 controller. */
-	FUNIT_CFG(SBC4, PLLP, 33333, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
+	/* SPI flash at 20MHz on SPI4 controller. */
+	FUNIT_CFG(SBC4, PLLP, 20000, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
 };
 
 void bootblock_mainboard_early_init(void)
diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c
index d481b87..493a221 100644
--- a/src/soc/nvidia/tegra132/spi.c
+++ b/src/soc/nvidia/tegra132/spi.c
@@ -210,7 +210,7 @@ static struct tegra_spi_channel * const to_tegra_spi(int bus) {
 static unsigned int tegra_spi_speed(unsigned int bus)
 {
 	/* FIXME: implement this properly, for now use max value (50MHz) */
-	return 50000000;
+	return 20000000;
 }
 
 int spi_claim_bus(struct spi_slave *slave)