[coreboot-gerrit] Patch set updated for coreboot: 4ad2dd1 arm64: Make SPSR exception masking on EL2 transition explicit

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10250

-gerrit

commit 4ad2dd1c9ad986013b6693c09c7fdc7f355609b6
Author: Julius Werner <jwerner at chromium.org>
Date:   Wed May 13 11:19:33 2015 -0700

    arm64: Make SPSR exception masking on EL2 transition explicit
    
    The configuration of SPSR bits that mask processor exceptions is kinda
    oddly hidden as an implict part of the transition() function right now.
    It would be odd but not impossible for programs to want to be entered
    with enabled exceptions, so let's move these bits to be explicitly set
    by the caller like the rest of SPSR instead.
    
    Also clear up some macro names. The SPSR[I] bit is currently defined as
    SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit
    actually *disables* (masks) interrupts. The fact that there is an
    additional SPSR_IRQ_MASK definition with the same value but a different
    purpose doesn't really help. There's rarely a point to have all three of
    xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so
    simplify this to a single definition per bit. (Other macros in
    lib_helpers.h should probably also be overhauled to conform, but I want
    to wait and see how many of them really stay relevant after upcoming
    changes first.)
    
    BRANCH=None
    BUG=None
    TEST=None
    
    Change-Id: Id126f70d365467e43b7f493c341542247e5026d2
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297
    Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/270785
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/arm64/boot.c                           |  2 +-
 src/arch/arm64/include/armv8/arch/lib_helpers.h | 17 +++++------------
 src/arch/arm64/transition.c                     | 10 ++--------
 3 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
index f67f825..226d8d7 100644
--- a/src/arch/arm64/boot.c
+++ b/src/arch/arm64/boot.c
@@ -37,7 +37,7 @@ static void run_payload(struct prog *prog)
 
 	doit = prog_entry(prog);
 	arg = prog_entry_arg(prog);
-	u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L);
+	u64 payload_spsr = SPSR_EXCEPTION_MASK | get_eret_el(EL2, SPSR_USE_L);
 
 	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr);
diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h
index 315a0c0..55eff27 100644
--- a/src/arch/arm64/include/armv8/arch/lib_helpers.h
+++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h
@@ -39,18 +39,11 @@
 #define SPSR_M_SHIFT         4
 #define SPSR_ERET_32         (1 << SPSR_M_SHIFT)
 #define SPSR_ERET_64         (0 << SPSR_M_SHIFT)
-#define SPSR_FIQ_SHIFT       6
-#define SPSR_FIQ_MASK        (0 << SPSR_FIQ_SHIFT)
-#define SPSR_FIQ_ENABLE      (1 << SPSR_FIQ_SHIFT)
-#define SPSR_IRQ_SHIFT       7
-#define SPSR_IRQ_MASK        (0 << SPSR_IRQ_SHIFT)
-#define SPSR_IRQ_ENABLE      (1 << SPSR_IRQ_SHIFT)
-#define SPSR_SERROR_SHIFT    8
-#define SPSR_SERROR_MASK     (0 << SPSR_SERROR_SHIFT)
-#define SPSR_SERROR_ENABLE   (1 << SPSR_SERROR_SHIFT)
-#define SPSR_DEBUG_SHIFT     9
-#define SPSR_DEBUG_MASK      (0 << SPSR_DEBUG_SHIFT)
-#define SPSR_DEBUG_ENABLE    (1 << SPSR_DEBUG_SHIFT)
+#define SPSR_FIQ             (1 << 6)
+#define SPSR_IRQ             (1 << 7)
+#define SPSR_SERROR          (1 << 8)
+#define SPSR_DEBUG           (1 << 9)
+#define SPSR_EXCEPTION_MASK  (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
 
 #define SCR_NS_SHIFT         0
 #define SCR_NS_MASK          (1 << SCR_NS_SHIFT)
diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c
index 523960e..8d549ef 100644
--- a/src/arch/arm64/transition.c
+++ b/src/arch/arm64/transition.c
@@ -21,9 +21,6 @@
 #include <arch/transition.h>
 #include <console/console.h>
 
-/* Mask out debug exceptions, serror, irq and fiq */
-#define SPSR_MASK   (SPSR_FIQ_MASK | SPSR_IRQ_MASK | SPSR_SERROR_MASK | \
-		     SPSR_DEBUG_MASK)
 /* Litte-endian, No XN-forced, Instr cache disabled,
  * Stack alignment disabled, Data and unified cache
  * disabled, Alignment check disabled, MMU disabled
@@ -101,10 +98,6 @@ void transition(struct exc_state *exc_state)
 		hcr_mask = HCR_LOWER_AARCH64;
 	}
 
-	/* SPSR: Mask out debug exceptions, serror, irq, fiq */
-	elx->spsr |= SPSR_MASK;
-	raw_write_spsr_current(elx->spsr);
-
 	/* SCR: Write to SCR if current EL is EL3 */
 	if (current_el == EL3) {
 		uint32_t scr = raw_read_scr_el3();
@@ -118,8 +111,9 @@ void transition(struct exc_state *exc_state)
 		raw_write_hcr_el2(hcr);
 	}
 
-	/* ELR: Write entry point of program */
+	/* ELR/SPSR: Write entry point and processor state of program */
 	raw_write_elr_current(elx->elr);
+	raw_write_spsr_current(elx->spsr);
 
 	/* SCTLR: Initialize EL with selected properties */
 	sctlr = raw_read_sctlr(elx_el);