[coreboot-gerrit] Patch set updated for coreboot: 052b467 pistashio: bump up romstage size

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10220

-gerrit

commit 052b46789c03b0f32967f611d1b3237dbe6edadd
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri May 15 16:54:17 2015 -0500

    pistashio: bump up romstage size
    
    Making large changes in pieces is leading to a little bloat.
    Bump up the romstage size temporarily so that jenkins will be
    happy.
    
    Change-Id: I6f9facb4ca488cf41741a3ed6d0ed7f66d4778b3
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index bc67447..ad1d1c5 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,8 +38,8 @@ SECTIONS
 	 * and then through the identity mapping in ROM stage.
 	 */
 	SRAM_START(0x1a000000)
-	ROMSTAGE(0x1a005000, 36K)
-	PRERAM_CBFS_CACHE(0x1a00e000, 72K)
+	ROMSTAGE(0x1a005000, 40K)
+	PRERAM_CBFS_CACHE(0x1a00f000, 68K)
 	SRAM_END(0x1a020000)
 
 	/* Bootblock executes out of KSEG0 and sets up the identity mapping.