[coreboot-gerrit] Patch set updated for coreboot: 48599ad Revert "pistashio: bump up romstage size"

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10222

-gerrit

commit 48599ad9a5fc4bde5ec5d83655db30393e02b58b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri May 15 16:56:27 2015 -0500

    Revert "pistashio: bump up romstage size"
    
    This reverts commit 701211a6e57a17ea861b4ad682dca7416fc9050e.
    
    Change-Id: Ib3e573548bff5c17ab30cfab3d833a2065d689c9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index ad1d1c5..bc67447 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,8 +38,8 @@ SECTIONS
 	 * and then through the identity mapping in ROM stage.
 	 */
 	SRAM_START(0x1a000000)
-	ROMSTAGE(0x1a005000, 40K)
-	PRERAM_CBFS_CACHE(0x1a00f000, 68K)
+	ROMSTAGE(0x1a005000, 36K)
+	PRERAM_CBFS_CACHE(0x1a00e000, 72K)
 	SRAM_END(0x1a020000)
 
 	/* Bootblock executes out of KSEG0 and sets up the identity mapping.