[coreboot-gerrit] New patch to review for coreboot: 4847fea util/inteltool: add broadwell support, fix GPIOs
Matt DeVillier (matt.devillier@gmail.com)
gerrit at coreboot.org
Thu May 14 17:53:31 CEST 2015
Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10204
-gerrit
commit 4847fea88c866f1580d462464ad48c5f383dc6b9
Author: Matt DeVillier <matt.devillier at gmail..com>
Date: Thu May 14 10:28:33 2015 -0500
util/inteltool: add broadwell support, fix GPIOs
- add handling for PCI IDs for Broadwell-U/Wildcat Point LP
- use same functions as Haswell-U/Lynx Point LP
- fix GPIO offsets, definitions per Intel specs
- fix address register maskings per Intel specs
Change-Id: I4ba2cc586666419b1fb7e35771fcab22d4c1232d
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
util/inteltool/gpio.c | 49 +++++++++++++++++-----------------------------
util/inteltool/inteltool.c | 2 ++
util/inteltool/inteltool.h | 2 ++
util/inteltool/memory.c | 1 +
util/inteltool/pcie.c | 4 ++++
util/inteltool/powermgt.c | 1 +
util/inteltool/rootcmplx.c | 3 ++-
util/inteltool/spi.c | 3 ++-
8 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index aaacd57..b04fbd6 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -298,12 +298,11 @@ static const gpio_default_t ip_pch_mobile_defaults[] = {
};
static const io_register_t lynxpoint_lp_gpio_registers[] = {
- { 0x00, 4, "GPIO_OWN1" }, // GPIO Ownership
- { 0x04, 4, "GPIO_OWN2" }, // GPIO Ownership
- { 0x08, 4, "GPIO_OWN3" }, // GPIO Ownership
- { 0x0c, 4, "RESERVED" }, // Reserved
- { 0x10, 2, "GPIPRIOQ2IOXAPIC" }, // GPI PIRQ[X:I] to IOxAPIC[39:24] Enable
- { 0x12, 2, "RESERVED" }, // Reserved
+ { 0x00, 4, "GPIO_USE_SEL" }, // GPIO Use Select
+ { 0x04, 4, "GPIO_IO_SEL" }, // GPIO I/O Select
+ { 0x08, 4, "RESERVED" }, // Reserved
+ { 0x0c, 4, "GPIO_LVL" }, // GPIO Level for I/O
+ { 0x10, 4, "RESERVED" }, // Reserved
{ 0x14, 4, "RESERVED" }, // Reserved
{ 0x18, 4, "GPO_BLINK" }, // GPIO Blink Enable
{ 0x1c, 4, "GP_SER_BLINK" }, // GP Serial Blink
@@ -311,17 +310,17 @@ static const io_register_t lynxpoint_lp_gpio_registers[] = {
{ 0x24, 4, "GP_SB_DATA" }, // GP Serial Blink Data
{ 0x28, 2, "GPI_NMI_EN" }, // GPI NMI Enable
{ 0x2a, 2, "GPI_NMI_STS" }, // GPI NMI Status
- { 0x2c, 4, "RESERVED" }, // Reserved
- { 0x30, 4, "GPI_ROUT" }, // GPI Interrupt Input Route
- { 0x34, 4, "RESERVED" }, // Reserved
- { 0x38, 4, "RESERVED" }, // Reserved
+ { 0x2c, 4, "GPI_INV" }, // GPIO Signal Invert
+ { 0x30, 4, "GPIO_USE_SEL2" }, // GPIO Use Select 2
+ { 0x34, 4, "GPIO_IO_SEL2" }, // GPIO I/O Select 2
+ { 0x38, 4, "GPIO_LVL2" }, // GPIO Level for I/O 2
{ 0x3C, 4, "RESERVED" }, // Reserved
- { 0x40, 4, "RESERVED" }, // Reserved
- { 0x44, 4, "RESERVED" }, // Reserved
- { 0x48, 4, "RESERVED" }, // Reserved
+ { 0x40, 4, "GPIO_USE_SEL3" }, // GPIO Use Select 3
+ { 0x44, 4, "GPIO_IO_SEL3" }, // GPIO I/O Select 3
+ { 0x48, 4, "GPIO_LVL3" }, // GPIO Level for I/O 3
{ 0x4C, 4, "RESERVED" }, // Reserved
- { 0x50, 4, "ALT_GPI_SMI_STS" }, // Alternate GPI SMI Status
- { 0x54, 4, "ALT_GPI_SMI_EN" }, // Alternate GPI SMI Enable
+ { 0x50, 4, "RESERVED" }, // Reserved
+ { 0x54, 4, "RESERVED" }, // Reserved
{ 0x58, 4, "RESERVED" }, // Reserved
{ 0x5C, 4, "RESERVED" }, // Reserved
{ 0x60, 4, "GP_RST_SEL1" }, // GPIO Reset Select 1
@@ -331,21 +330,7 @@ static const io_register_t lynxpoint_lp_gpio_registers[] = {
{ 0x70, 4, "RESERVED" }, // Reserved
{ 0x74, 4, "RESERVED" }, // Reserved
{ 0x78, 4, "RESERVED" }, // Reserved
- { 0x7c, 4, "GPIO_GC" }, // GPIO Global Configuration
- { 0x80, 4, "GPI_IS[31:0]" }, // GPI Interrupt Status [31:0]
- { 0x84, 4, "GPI_IS[63:32]" }, // GPI Interrupt Status [63:32]
- { 0x88, 4, "GPI_IS[94:64]" }, // GPI Interrupt Status [94:64]
- { 0x8C, 4, "RESERVED" }, // Reserved
- { 0x90, 4, "GPI_IE[31:0]" }, // GPI Interrupt Enable [31:0]
- { 0x94, 4, "GPI_IE[63:32]" }, // GPI Interrupt Enable [63:32]
- { 0x98, 4, "GPI_IE[94:64]" }, // GPI Interrupt Enable [94:64]
- { 0x9C, 4, "RESERVED" }, // Reserved
-/* { 0x100, 4, "GPnCONFIGA" }, // GPIO Configuration A Register (n = 0) */
-/* { 0x104, 4, "GPnCONFIGB" }, // GPIO Configuration B Register (n = 0) */
-/* { ... } GPIO size = 95 */
-/* { 0x3f0, 4, "GPnCONFIGA" }, // GPIO Configuration A Register (n = 94) */
-/* { 0x3f4, 4, "GPnCONFIGB" }, // GPIO Configuration B Register (n = 94) */
-
+ { 0x7c, 4, "RESERVED" }, // Reserved
};
/* Default values for Cougar Point desktop chipsets */
@@ -856,7 +841,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
- gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+ case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
+ gpiobase = pci_read_word(sb, 0x48) & 0xff80;
gpio_registers = lynxpoint_lp_gpio_registers;
size = ARRAY_SIZE(lynxpoint_lp_gpio_registers);
break;
@@ -1050,6 +1036,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
+ case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
for (i = 0; i < 95; i++) {
io_register_t tmp_gpio;
char gpio_name[32];
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 1a6bda2..a3712c5 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -84,6 +84,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M, "4th generation (Haswell family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3, "4th generation (Haswell family) Core Processor (Xeon E3 v3)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U, "4th generation (Haswell family) Core Processor ULT" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
/* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
@@ -163,6 +164,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, "Lynx Point Low Power Full Featured Engineering Sample" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, "Lynx Point Low Power Premium SKU" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, "Lynx Point Low Power Base SKU" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP, "Wildcat Point Low Power SKU" },
{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" },
};
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 3014b3e..501193d 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -112,6 +112,7 @@
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
@@ -173,6 +174,7 @@
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
+#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 3aa3e4f..950d4a3 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -216,6 +216,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
+ case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 6fa94e9..eaf0cd2 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -216,8 +216,10 @@ int print_epbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
+ case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
+ epbar_phys &= 0x0000007ffffff000UL; /* 38:12 */
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810_DC:
@@ -321,6 +323,7 @@ int print_dmibar(struct pci_dev *nb)
dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
break;
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
+ case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
dmi_registers = haswell_ult_dmi_registers;
size = ARRAY_SIZE(haswell_ult_dmi_registers);
dmibar_phys = pci_read_long(nb, 0x68);
@@ -418,6 +421,7 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
+ case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break;
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index 2cefabe..865cfba 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -705,6 +705,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
+ case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = pch_pm_registers;
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index f57e773..6f26186 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -98,7 +98,8 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
- rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
+ case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
+ rcba_phys = pci_read_long(sb, 0xf0) & 0xffffc000;
break;
case PCI_DEVICE_ID_INTEL_ICH:
case PCI_DEVICE_ID_INTEL_ICH0:
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index e4a77b6..396728e 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -170,7 +170,8 @@ int print_spibar(struct pci_dev *sb) {
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
- rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
+ case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
+ rcba_phys = pci_read_long(sb, 0xf0) & 0xffffc000;
size = ARRAY_SIZE(spi_bar_registers);
spi_register = spi_bar_registers;
break;
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