[coreboot-gerrit] New patch to review for coreboot: cca38ba mainboard/intel/d510mo: Add Intel D510MO mainboard
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Sun May 3 15:10:58 CEST 2015
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10074
-gerrit
commit cca38ba7c079144407f59b5651bec5aec7b4c9e5
Author: Damien Zammit <damien at zamaudio.com>
Date: Sun May 3 20:16:26 2015 +1000
mainboard/intel/d510mo: Add Intel D510MO mainboard
Board has no raminit, (pineview northbridge).
Board boots to UART console
Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/mainboard/intel/Kconfig | 3 +
src/mainboard/intel/d510mo/Kconfig | 56 ++++++++++++++++++
src/mainboard/intel/d510mo/board_info.txt | 5 ++
src/mainboard/intel/d510mo/devicetree.cb | 77 +++++++++++++++++++++++++
src/mainboard/intel/d510mo/dsdt.asl | 55 ++++++++++++++++++
src/mainboard/intel/d510mo/hda_verb.c | 7 +++
src/mainboard/intel/d510mo/romstage.c | 95 +++++++++++++++++++++++++++++++
7 files changed, 298 insertions(+)
diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index d2dd7ce..98171c3 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -9,6 +9,8 @@ config BOARD_INTEL_BAYLEYBAY_FSP
bool "Bayley Bay FSP-based CRB"
config BOARD_INTEL_COUGAR_CANYON2
bool "Cougar Canyon 2 CRB"
+config BOARD_INTEL_D510MO
+ bool "D510MO"
config BOARD_INTEL_D810E2CB
bool "D810E2CB"
config BOARD_INTEL_D945GCLF
@@ -39,6 +41,7 @@ endchoice
source "src/mainboard/intel/bakersport_fsp/Kconfig"
source "src/mainboard/intel/bayleybay_fsp/Kconfig"
source "src/mainboard/intel/cougar_canyon2/Kconfig"
+source "src/mainboard/intel/d510mo/Kconfig"
source "src/mainboard/intel/d810e2cb/Kconfig"
source "src/mainboard/intel/d945gclf/Kconfig"
source "src/mainboard/intel/eagleheights/Kconfig"
diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
new file mode 100644
index 0000000..9499a69
--- /dev/null
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -0,0 +1,56 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Damien Zammit <damien at zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+if BOARD_INTEL_D510MO
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_INTEL_SOCKET_ATOM_D5XX
+ select NORTHBRIDGE_INTEL_PINEVIEW
+ #select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627THG
+ #select HAVE_PIRQ_TABLE
+ select HAVE_ACPI_TABLES
+ select BROKEN_CAR_MIGRATE
+ #select USE_WATCHDOG_ON_BOOT
+ #select UDELAY_TSC
+ #select EARLY_CBMEM_INIT
+ select BOARD_ROMSIZE_KB_1024
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe0000000
+
+config CBFS_SIZE
+ hex "Size of CBFS filesystem in ROM"
+ default 0x100000
+
+config MAINBOARD_DIR
+ string
+ default intel/d510mo
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "D510MO"
+
+config IRQ_SLOT_COUNT
+ int
+ default 7
+
+endif # BOARD_INTEL_D510MO
diff --git a/src/mainboard/intel/d510mo/board_info.txt b/src/mainboard/intel/d510mo/board_info.txt
new file mode 100644
index 0000000..192798a
--- /dev/null
+++ b/src/mainboard/intel/d510mo/board_info.txt
@@ -0,0 +1,5 @@
+Category: desktop
+Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
new file mode 100644
index 0000000..4a1a3d2
--- /dev/null
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -0,0 +1,77 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+chip northbridge/intel/pineview # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/model_106cx # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # Host Bridge
+ device pci 2.0 on end # Integrated graphics controller
+ chip southbridge/intel/i82801gx # Southbridge
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ device pci 1c.2 on end # PCIe 3
+ device pci 1c.3 on end # PCIe 4
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.3 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA bridge
+ chip superio/winbond/w83627thg # Super I/O
+ device pnp 4e.0 off end # Floppy
+ device pnp 4e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 4e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.5 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 4e.a on end # ACPI
+ device pnp 4e.b on # HWM
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1f.1 off end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMbus
+ device pci 1f.4 off end
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ end
+ end
+end
diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl
new file mode 100644
index 0000000..b6a1b8d
--- /dev/null
+++ b/src/mainboard/intel/d510mo/dsdt.asl
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ // Some generic macros
+ //#include "acpi/platform.asl"
+
+ // global NVS and variables
+ //#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ //#include <southbridge/intel/i82801gx/acpi/platform.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ //#include "acpi/mainboard.asl"
+
+ // Thermal Zone
+ //#include "acpi/thermal.asl"
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ //#include <northbridge/intel/pineview/acpi/i945.asl>
+ //#include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ //#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c
new file mode 100644
index 0000000..072a306
--- /dev/null
+++ b/src/mainboard/intel/d510mo/hda_verb.c
@@ -0,0 +1,7 @@
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[0] = {};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
new file mode 100644
index 0000000..71ba858
--- /dev/null
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include "southbridge/intel/i82801gx/i82801gx.h"
+//#include "northbridge/intel/pineview/raminit.h"
+#include "northbridge/intel/pineview/pineview.h"
+#include "cpu/x86/bist.h"
+#include <superio/winbond/w83627thg/w83627thg.h>
+#include <superio/winbond/common/winbond.h>
+#include <lib.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
+#define SUPERIO_DEV PNP_DEV(0x4e, 0)
+
+#include <cpu/intel/romstage.h>
+
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+ device_t dev;
+
+ /* Southbridge GPIOs. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
+ pci_write_config8(dev, GPIO_CNTL, 0x10);
+
+ outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+ outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+ outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+ outl(0x000000fe, DEFAULT_GPIOBASE + 0x30);
+ outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);
+ outl(0x000300f3, DEFAULT_GPIOBASE + 0x38);
+}
+
+static void nm10_enable_lpc(void)
+{
+ // disable Serial IRQ
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00); //d0
+ // decode range
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ // decode range
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
+ CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
+
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+}
+
+void main(unsigned long bist)
+{
+ //const u8 spd_addrmap[4] = { 0x50, 0x51 };
+
+ // Disable watchdog timer
+ RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
+
+ // Set southbridge and Super I/O GPIOs.
+ mb_gpio_init();
+
+ nm10_enable_lpc();
+ winbond_enable_serial(SERIAL_DEV, 0x3f8);
+ console_init();
+
+ report_bist_failure(bist);
+ enable_smbus();
+ die("Waiting here\n");
+ //i945_early_initialization();
+ //sdram_initialize(0, spd_addrmap);
+}
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