[coreboot-gerrit] Patch set updated for coreboot: 1b0c8d7 superio/smsc/sch311x: Add support for SCH3112, SCH3114 and SCH3116 Super I/Os
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Sun May 3 09:46:43 CEST 2015
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7626
-gerrit
commit 1b0c8d73fc6ee2a48afe60990454d040775e2f85
Author: Damien Zammit <damien at zamaudio.com>
Date: Tue Dec 2 20:24:31 2014 +1100
superio/smsc/sch311x: Add support for SCH3112, SCH3114 and SCH3116 Super I/Os
Includes a command to share all 2-6 serial ports among a single IRQ.
Tested on Intel D510MO (not in tree yet)
Change-Id: I759d458bb03e145a68fe04617521ce079cc2be2f
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/superio/smsc/Kconfig | 2 +
src/superio/smsc/Makefile.inc | 1 +
src/superio/smsc/sch311x/Makefile.inc | 21 ++++++++
src/superio/smsc/sch311x/sch311x.h | 36 +++++++++++++
src/superio/smsc/sch311x/sch311x_early_init.c | 73 +++++++++++++++++++++++++++
src/superio/smsc/sch311x/superio.c | 68 +++++++++++++++++++++++++
6 files changed, 201 insertions(+)
diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
index 6aaa112..a47d127 100644
--- a/src/superio/smsc/Kconfig
+++ b/src/superio/smsc/Kconfig
@@ -47,5 +47,7 @@ config SUPERIO_SMSC_SMSCSUPERIO
select SUPERIO_WANTS_14MHZ_CLOCK
config SUPERIO_SMSC_SIO1036
bool
+config SUPERIO_SMSC_SCH311X
+ bool
config SUPERIO_SMSC_SCH4037
bool
diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc
index a89b6ac..2397d6c 100644
--- a/src/superio/smsc/Makefile.inc
+++ b/src/superio/smsc/Makefile.inc
@@ -32,4 +32,5 @@ subdirs-y += kbc1100
subdirs-y += mec1308
subdirs-y += smscsuperio
subdirs-y += sio1036
+subdirs-y += sch311x
subdirs-y += sch4037
diff --git a/src/superio/smsc/sch311x/Makefile.inc b/src/superio/smsc/sch311x/Makefile.inc
new file mode 100644
index 0000000..de0e724
--- /dev/null
+++ b/src/superio/smsc/sch311x/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Damien Zammit <damien at zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-$(CONFIG_SUPERIO_SMSC_SCH311X) += sch311x_early_init.c
+ramstage-$(CONFIG_SUPERIO_SMSC_SCH311X) += superio.c
diff --git a/src/superio/smsc/sch311x/sch311x.h b/src/superio/smsc/sch311x/sch311x.h
new file mode 100644
index 0000000..f9cd089
--- /dev/null
+++ b/src/superio/smsc/sch311x/sch311x.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_SCH_311X_H
+#define SUPERIO_SCH_311X_H
+
+#define SCH311X_FDD 0 /* FDD */
+#define SCH311X_LPT 3 /* LPT */
+#define SMSCSUPERIO_SP1 4 /* Com1 */
+#define SMSCSUPERIO_SP2 5 /* Com2 */
+#define SCH311X_KBC 7 /* KBC */
+#define SCH311X_RUNTIME 0x0A /* Runtime */
+#define SMSCSUPERIO_SP3 0x0B /* Com3 */
+#define SMSCSUPERIO_SP4 0x0C /* Com4 */
+#define SMSCSUPERIO_SP5 0x0D /* Com5 */
+#define SMSCSUPERIO_SP6 0x0E /* Com6 */
+
+void sch311x_early_init(unsigned port);
+
+#endif /* SUPERIO_SCH_311X_H */
diff --git a/src/superio/smsc/sch311x/sch311x_early_init.c b/src/superio/smsc/sch311x/sch311x_early_init.c
new file mode 100644
index 0000000..4b0db47
--- /dev/null
+++ b/src/superio/smsc/sch311x/sch311x_early_init.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
+#include "sch311x.h"
+
+static void pnp_enter_conf_state(pnp_devfn_t dev)
+{
+ unsigned port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(pnp_devfn_t dev)
+{
+ unsigned port = dev >> 8;
+ outb(0xaa, port);
+}
+
+void sch311x_early_init(unsigned port)
+{
+ pnp_devfn_t dev;
+
+ dev = PNP_DEV(port, SMSCSUPERIO_SP1);
+ pnp_enter_conf_state(dev);
+
+ /* Auto power management */
+ pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
+ pnp_write_config(dev, 0x23, 0 );
+
+ /* Enable SMSC UART 0 */
+ dev = PNP_DEV(port, SMSCSUPERIO_SP1);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+
+ pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
+ pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
+
+ /* Enable High speed, disable MIDI support,
+ * Share 1x IRQ among all serial ports */
+ pnp_write_config(dev, 0xF0, 0xC2);
+ pnp_set_enable(dev, 1);
+
+ /* Enable keyboard */
+ dev = PNP_DEV(port, SCH311X_KBC);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
+ pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
+ pnp_set_enable(dev, 1);
+
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/smsc/sch311x/superio.c b/src/superio/smsc/sch311x/superio.c
new file mode 100644
index 0000000..e28ff77
--- /dev/null
+++ b/src/superio/smsc/sch311x/superio.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* RAM driver for the SMSC SCH311X Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+
+#include "sch311x.h"
+
+static void sch311x_init(struct device *dev)
+{
+ if (!dev->enabled) {
+ return;
+ }
+
+ switch(dev->path.pnp.device) {
+ case SCH311X_KBC:
+ pc_keyboard_init();
+ break;
+ default:
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = sch311x_init,
+ .ops_pnp_mode = &pnp_conf_mode_55_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, SCH311X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_smsc_sch311x_ops = {
+ CHIP_NAME("SMSC SCH311x Super I/O")
+ .enable_dev = enable_dev,
+};
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