[coreboot-gerrit] Patch merged into coreboot/master: b738913 northbridge/intel/fsp_rangeley: Correct MMIO size setting

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit b738913ce050cd5a61d902e7024d4881cdb1ae59
Author: Dave Frodin <dave.frodin at se-eng.com>
Date:   Fri May 1 09:17:43 2015 -0600

    northbridge/intel/fsp_rangeley: Correct MMIO size setting
    
    The Rangeley chipset has the MMIO PCI config space feature
    enabled at 0xe0000000-0xefffffff. This is a 256MB space
    which covers all of config space. The ACPI table for
    this space only defines it as being 64MB. This change
    fixes that setting.
    
    Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e
    Signed-off-by: Dave Frodin <dave.frodin at se-eng.com>
    Reviewed-on: http://review.coreboot.org/10047
    Reviewed-by: Marc Jones <marc.jones at se-eng.com>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/10047 for details.

-gerrit