[coreboot-gerrit] New patch to review for coreboot: 252ce9b Nyans: replace cpu_reset with hard_reset
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Tue Mar 31 22:55:24 CEST 2015
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9179
-gerrit
commit 252ce9b3af6e36e8be7d47ec11fa6b8b71384322
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date: Fri Aug 15 17:07:39 2014 -0700
Nyans: replace cpu_reset with hard_reset
The existing cpu_reset does board-wide reset, thus, should be renamed.
BUG=none
BRANCH=none
TEST=Built firmware for Nyans. Ran faft on Blaze.
Original-Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
Original-Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9
Original-Reviewed-on: https://chromium-review.googlesource.com/212982
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri at chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri at chromium.org>
(cherry picked from commit 29753b9c1dfe7ecd156042d69b74e9fe4244f455)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: I98eca40c50637bda01a9029a904bca6880cd081f
---
src/mainboard/google/nyan/Makefile.inc | 1 +
src/mainboard/google/nyan/pmic.c | 4 ++--
src/mainboard/google/nyan/reset.c | 5 ++---
src/mainboard/google/nyan/reset.h | 25 -------------------------
src/mainboard/google/nyan/romstage.c | 4 ++--
src/mainboard/google/nyan_big/Makefile.inc | 1 +
src/mainboard/google/nyan_big/pmic.c | 4 ++--
src/mainboard/google/nyan_big/reset.c | 5 ++---
src/mainboard/google/nyan_big/reset.h | 25 -------------------------
src/mainboard/google/nyan_big/romstage.c | 4 ++--
src/mainboard/google/nyan_blaze/Makefile.inc | 1 +
src/mainboard/google/nyan_blaze/pmic.c | 4 ++--
src/mainboard/google/nyan_blaze/reset.c | 5 ++---
src/mainboard/google/nyan_blaze/reset.h | 25 -------------------------
src/mainboard/google/nyan_blaze/romstage.c | 4 ++--
src/soc/nvidia/tegra124/Kconfig | 1 +
16 files changed, 22 insertions(+), 96 deletions(-)
diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
index de1e127..7ac11e8 100644
--- a/src/mainboard/google/nyan/Makefile.inc
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -38,6 +38,7 @@ romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += early_configs.c
+ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c
index 2a65719..b290871 100644
--- a/src/mainboard/google/nyan/pmic.c
+++ b/src/mainboard/google/nyan/pmic.c
@@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
-#include "reset.h"
+#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
- cpu_reset();
+ hard_reset();
} else {
if (do_delay)
udelay(500);
diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c
index 7f1fff9..05cca27 100644
--- a/src/mainboard/google/nyan/reset.c
+++ b/src/mainboard/google/nyan/reset.c
@@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
+#include <reset.h>
-#include "reset.h"
-
-void cpu_reset(void)
+void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);
diff --git a/src/mainboard/google/nyan/reset.h b/src/mainboard/google/nyan/reset.h
deleted file mode 100644
index debe838..0000000
--- a/src/mainboard/google/nyan/reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-
-void cpu_reset(void);
-
-#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index fffe0de..1ff500b 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <mainboard/google/nyan/reset.h>
+#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -79,7 +79,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
- cpu_reset();
+ hard_reset();
}
cbmem_initialize_empty();
diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc
index 1eb5404..8ca495c 100644
--- a/src/mainboard/google/nyan_big/Makefile.inc
+++ b/src/mainboard/google/nyan_big/Makefile.inc
@@ -37,6 +37,7 @@ romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += early_configs.c
+ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c
index ed855f1..c89db28 100644
--- a/src/mainboard/google/nyan_big/pmic.c
+++ b/src/mainboard/google/nyan_big/pmic.c
@@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
-#include "reset.h"
+#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
- cpu_reset();
+ hard_reset();
} else {
if (do_delay)
udelay(500);
diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c
index 7f1fff9..05cca27 100644
--- a/src/mainboard/google/nyan_big/reset.c
+++ b/src/mainboard/google/nyan_big/reset.c
@@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
+#include <reset.h>
-#include "reset.h"
-
-void cpu_reset(void)
+void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);
diff --git a/src/mainboard/google/nyan_big/reset.h b/src/mainboard/google/nyan_big/reset.h
deleted file mode 100644
index debe838..0000000
--- a/src/mainboard/google/nyan_big/reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-
-void cpu_reset(void);
-
-#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index fffe0de..1ff500b 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <mainboard/google/nyan/reset.h>
+#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -79,7 +79,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
- cpu_reset();
+ hard_reset();
}
cbmem_initialize_empty();
diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc
index 8cfa298..dc998d1 100644
--- a/src/mainboard/google/nyan_blaze/Makefile.inc
+++ b/src/mainboard/google/nyan_blaze/Makefile.inc
@@ -41,6 +41,7 @@ romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c
index ed855f1..c89db28 100644
--- a/src/mainboard/google/nyan_blaze/pmic.c
+++ b/src/mainboard/google/nyan_blaze/pmic.c
@@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
-#include "reset.h"
+#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
- cpu_reset();
+ hard_reset();
} else {
if (do_delay)
udelay(500);
diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c
index 7f1fff9..05cca27 100644
--- a/src/mainboard/google/nyan_blaze/reset.c
+++ b/src/mainboard/google/nyan_blaze/reset.c
@@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
+#include <reset.h>
-#include "reset.h"
-
-void cpu_reset(void)
+void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);
diff --git a/src/mainboard/google/nyan_blaze/reset.h b/src/mainboard/google/nyan_blaze/reset.h
deleted file mode 100644
index debe838..0000000
--- a/src/mainboard/google/nyan_blaze/reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-
-void cpu_reset(void);
-
-#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index 65596a2..fca705d 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <mainboard/google/nyan/reset.h>
+#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -82,7 +82,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
- cpu_reset();
+ hard_reset();
}
cbmem_initialize_empty();
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 4fcc6b4..acc6e7e 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -6,6 +6,7 @@ config SOC_NVIDIA_TEGRA124
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_UART_SPECIAL
+ select HAVE_HARD_RESET
select BOOTBLOCK_CONSOLE
select ARM_BOOTBLOCK_CUSTOM
select ARM_LPAE
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