[coreboot-gerrit] New patch to review for coreboot: 2e97f82 northbridge/amd/amdmct: Pack MCT and DCT info structs

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9158

-gerrit

commit 2e97f82b2da643ee1120ff72141737d4ba0bfd58
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Sun Mar 29 16:21:23 2015 -0500

    northbridge/amd/amdmct: Pack MCT and DCT info structs
    
    This allows safe access of romstage MCT values from ramstage
    
    Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdmct/mct/mct_d.h      | 4 ++--
 src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index 0a1f925..0c6df6c 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -260,7 +260,7 @@ struct MCTStatStruc {
 				      of sub 4GB dram hole for HW remapping.*/
 	u32 Sub4GCacheTop;	/* If not zero, the 32-bit top of cacheable memory.*/
 	u32 SysLimit;		/* LIMIT[39:8] (system address)*/
-};
+} __attribute__((packed));
 
 /*=============================================================================
 	Global MCT Configuration Status Word (GStatus)
@@ -512,7 +512,7 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u32 dev_map;
 	u32 dev_dct;
 	u32 dev_nbmisc;
-};
+} __attribute__((packed));
 
 /*===============================================================================
 	Local Error Status Codes (DCTStatStruc.ErrCode)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index 42cca26..8e73afe 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -287,7 +287,7 @@ struct MCTStatStruc {
 				      of sub 4GB dram hole for HW remapping.*/
 	u32 Sub4GCacheTop;	/* If not zero, the 32-bit top of cacheable memory.*/
 	u32 SysLimit;		/* LIMIT[39:8] (system address)*/
-};
+} __attribute__((packed));
 
 /*=============================================================================
 	Global MCT Configuration Status Word (GStatus)
@@ -575,7 +575,7 @@ struct DCTStatStruc {		/* A per Node structure*/
 	struct _sMCTStruct s_C_MCTPtr;
 	struct _sDCTStruct s_C_DCTPtr[2];
 	/* struct _sDCTStruct s_C_DCT1Ptr[8]; */
-};
+} __attribute__((packed));
 
 /*===============================================================================
 	Local Error Status Codes (DCTStatStruc.ErrCode)