[coreboot-gerrit] New patch to review for coreboot: 57b2593 northbridge/amd/amdfam10: Collect DIMM information for ramstage use
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Sat Mar 28 04:56:10 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9137
-gerrit
commit 57b2593cb46a857771236fc817abea2e34e817b7
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Fri Mar 27 22:50:09 2015 -0500
northbridge/amd/amdfam10: Collect DIMM information for ramstage use
Allow MCT information structures to be copied to cbmem
Retrieve DIMM vendor, model, and serial information
Allow maximum installable memory to be set via devicetree
Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/northbridge/amd/amdfam10/amdfam10.h | 1 +
src/northbridge/amd/amdfam10/amdfam10_util.c | 1 +
src/northbridge/amd/amdfam10/chip.h | 29 +++++
src/northbridge/amd/amdfam10/northbridge.c | 176 ++++++++++++++++++++++++++
src/northbridge/amd/amdfam10/raminit_amdmct.c | 25 ++++
src/northbridge/amd/amdmct/mct/mct_d.c | 28 +++-
src/northbridge/amd/amdmct/mct/mct_d.h | 31 +++++
src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +-
8 files changed, 290 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index a77d036..238c45f 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -977,6 +977,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#include "raminit.h"
+#include "../amdmct/wrappers/mcti.h"
#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
#include "../amdmct/mct_ddr3/mct_d.h"
#else
diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
index 2726b28..9788e54 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -21,6 +21,7 @@
#include <console/console.h>
#include <arch/cpu.h>
+#include "northbridge/amd/amdmct/wrappers/mcti.h"
#include <northbridge/amd/amdmct/mct/mct_d.h>
#include <northbridge/amd/amdmct/amddefs.h>
diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h
new file mode 100644
index 0000000..ab853d6
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/chip.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AMD_FAM10_CHIP_H_
+#define _AMD_FAM10_CHIP_H_
+
+#include <stdint.h>
+
+struct northbridge_amd_amdfam10_config {
+ uint64_t maximum_memory_capacity;
+};
+
+#endif /* _AMD_FAM10_CHIP_H_ */
\ No newline at end of file
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 9206de7..1662e28 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -28,6 +28,7 @@
#include <stdlib.h>
#include <string.h>
#include <lib.h>
+#include <smbios.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
@@ -43,6 +44,7 @@
#include "northbridge.h"
#include "amdfam10.h"
#include "ht_config.h"
+#include "chip.h"
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
#include <cpu/amd/model_10xxx_rev.h>
@@ -945,6 +947,177 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
return max;
}
+#if CONFIG_GENERATE_SMBIOS_TABLES
+static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *current)
+{
+ struct amdmct_memory_info *mem_info;
+ mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO);
+ if (mem_info == NULL)
+ return 0; /* can't find amdmct information in cbmem */
+
+ struct device *dev = get_node_pci(0, 0);
+ struct northbridge_amd_amdfam10_config *config = dev->chip_info;
+
+ int node;
+ int slot;
+
+ struct smbios_type16 *t = (struct smbios_type16 *)*current;
+ int len = sizeof(struct smbios_type16);
+
+ memset(t, 0, sizeof(struct smbios_type16));
+ t->type = SMBIOS_PHYS_MEMORY_ARRAY;
+ t->handle = handle;
+ t->length = len - 2;
+ t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
+ t->use = MEMORY_ARRAY_USE_SYSTEM;
+ t->memory_error_correction = MEMORY_ARRAY_ECC_NONE;
+ if ((mem_info->ecc_enabled)
+ && (mem_info->mct_stat.GStatus & (1 << GSB_ECCDIMMs))
+ && !(mem_info->mct_stat.GStatus & (1 << GSB_DramECCDis)))
+ /* Single-bit ECC enabled */
+ t->memory_error_correction = MEMORY_ARRAY_ECC_SINGLE_BIT;
+ t->maximum_capacity = config->maximum_memory_capacity / 1024; /* Convert to kilobytes */
+ t->memory_error_information_handle = 0xFFFE; /* no error information handle available */
+
+ t->number_of_memory_devices = 0;
+ /* Check all nodes for installed DIMMs */
+ for (node = 0; node < MAX_NODES_SUPPORTED; node++)
+ /* Check all slots for installed DIMMs */
+ for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++)
+ if (mem_info->dct_stat[node].DIMMPresent & (1 << slot))
+ /* Found an installed DIMM; increment count */
+ t->number_of_memory_devices++;
+
+ *current += len;
+ *count += 1;
+ return len;
+}
+
+static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed)
+{
+ switch (speed) {
+ case 1:
+ return 200;
+ case 2:
+ return 266;
+ case 3:
+ return 333;
+ case 4:
+ return 400;
+ case 5:
+ return 533;
+ default:
+ return 0;
+ }
+}
+
+static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, unsigned long *current)
+{
+ struct amdmct_memory_info *mem_info;
+ mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO);
+ if (mem_info == NULL)
+ return 0; /* can't find amdmct information in cbmem */
+
+ int single_len;
+ int len = 0;
+ int node;
+ int slot;
+
+ /* Check all nodes for installed DIMMs */
+ for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
+ /* Get configured RAM bus speed */
+ uint16_t speed;
+ speed = amdmct_mct_speed_enum_to_mhz(mem_info->dct_stat[node].Speed);
+
+ /* Get maximum RAM bus speed */
+ uint16_t max_speed;
+ max_speed = amdmct_mct_speed_enum_to_mhz(mem_info->dct_stat[node].DIMMAutoSpeed);
+
+ /* Check all slots for installed DIMMs */
+ for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) {
+ if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) {
+ /* Found an installed DIMM; populate tables */
+ struct smbios_type17 *t = (struct smbios_type17 *)*current;
+ char string_buffer[256];
+
+ /* Initialize structure */
+ memset(t, 0, sizeof(struct smbios_type17));
+
+ /* Calculate the total module size in bytes:
+ * Primary data width * 2^(#rows) * 2^(#cols) * #banks * #ranks
+ */
+ uint8_t width, rows, cols, banks, ranks;
+ width = 8;
+ rows = mem_info->dct_stat[node].DimmRows[slot];
+ cols = mem_info->dct_stat[node].DimmCols[slot];
+ ranks = mem_info->dct_stat[node].DimmRanks[slot];
+ banks = mem_info->dct_stat[node].DimmBanks[slot];
+ uint64_t dimm_size_bytes = width * (1ULL << rows) * (1ULL << cols) * banks * ranks;
+
+ memset(t, 0, sizeof(struct smbios_type17));
+ t->type = SMBIOS_MEMORY_DEVICE;
+ t->handle = handle;
+ t->phys_memory_array_handle = parent_handle;
+ t->length = sizeof(struct smbios_type17) - 2;
+ if (dimm_size_bytes > 0x800000000) {
+ t->size = 0x7FFF;
+ t->extended_size = dimm_size_bytes;
+ }
+ else {
+ t->size = dimm_size_bytes / (1024*1024);
+ t->size &= (~0x8000); /* size specified in megabytes */
+ }
+ t->data_width = 64;
+ if (mem_info->dct_stat[node].DimmECCPresent & (1 << slot))
+ t->total_width = 72;
+ else
+ t->total_width = 64;
+ t->attributes = 0;
+ t->attributes |= ranks & 0xf; /* rank number is stored in the lowest 3 bits of the attributes field */
+ t->form_factor = MEMORY_FORMFACTOR_DIMM;
+ snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1);
+ t->device_locator = smbios_add_string(t->eos, string_buffer);
+ t->memory_type = MEMORY_TYPE_DDR2;
+ t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS;
+ if (mem_info->dct_stat[node].DimmRegistered[slot])
+ t->type_detail |= MEMORY_TYPE_DETAIL_REGISTERED;
+ else
+ t->type_detail |= MEMORY_TYPE_DETAIL_UNBUFFERED;
+ t->speed = max_speed;
+ t->clock_speed = speed;
+ smbios_fill_dimm_manufacturer_from_id(mem_info->dct_stat[node].DimmManufacturerID[slot], t);
+ t->part_number = smbios_add_string(t->eos, mem_info->dct_stat[node].DimmPartNumber[slot]);
+ if (mem_info->dct_stat[node].DimmSerialNumber[slot] == 0) {
+ t->serial_number = smbios_add_string(t->eos, "None");
+ }
+ else {
+ snprintf(string_buffer, sizeof (string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]);
+ t->serial_number = smbios_add_string(t->eos, string_buffer);
+ }
+ t->memory_error_information_handle = 0xFFFE; /* no error information handle available */
+ single_len = t->length + smbios_string_table_len(t->eos);
+ len += single_len;
+ *current += single_len;
+ handle++;
+ *count += 1;
+ }
+ }
+ }
+
+ return len;
+}
+
+static int amdfam10_get_smbios_data(device_t dev, int *handle, unsigned long *current)
+{
+ int len;
+ int count = 0;
+ len = amdfam10_get_smbios_data16(&count, *handle, current);
+ len += amdfam10_get_smbios_data17(&count, *handle+1, *handle, current);
+ *handle += count;
+ return len;
+}
+#endif
+
static struct device_operations pci_domain_ops = {
.read_resources = amdfam10_domain_read_resources,
.set_resources = amdfam10_domain_set_resources,
@@ -952,6 +1125,9 @@ static struct device_operations pci_domain_ops = {
.init = NULL,
.scan_bus = amdfam10_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
+#if CONFIG_GENERATE_SMBIOS_TABLES
+ .get_smbios_data = amdfam10_get_smbios_data,
+#endif
};
static void sysconf_init(device_t dev) // first node
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 02dc956..b71733d 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -204,3 +204,28 @@ static void raminit_amdmct(struct sys_info *sysinfo)
printk(BIOS_DEBUG, "raminit_amdmct end:\n");
}
+
+static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
+{
+ /* Save memory info structures for use in ramstage */
+ size_t i;
+ struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
+ struct DCTStatStruc *pDCTstatA = 0;
+
+ if (pMCTstat && sysinfo->DCTstatA) {
+ /* Initialize memory */
+ struct amdmct_memory_info* mem_info;
+ mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info));
+ memset(mem_info, 0, sizeof(struct amdmct_memory_info));
+
+ /* Copy data */
+ memcpy(&mem_info->mct_stat, &(sysinfo->MCTstat), sizeof(struct MCTStatStruc));
+ for (i = 0; i < MAX_NODES_SUPPORTED; i++) {
+ pDCTstatA = sysinfo->DCTstatA + i;
+ if (pDCTstatA)
+ memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc));
+ }
+ mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP);
+ mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub);
+ }
+}
\ No newline at end of file
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index bf832da..64cb1bc 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -2122,7 +2122,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
* DATABload=number of ranks on the "B" bus slots.
*/
- u16 i, j;
+ u16 i, j, k;
u8 smbaddr, Index;
u16 Checksum;
u8 SPDCtrl;
@@ -2183,10 +2183,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
pDCTstat->DIMMValid |= 1 << i;
}
}
+ /* Get module information for SMBIOS */
+ if (pDCTstat->DIMMValid & (1 << i)) {
+ pDCTstat->DimmManufacturerID[i] = 0;
+ for (k = 0; k < 8; k++)
+ pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8);
+ for (k = 0; k < SPD_PARTN_LENGTH; k++)
+ pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k);
+ pDCTstat->DimmRevisionNumber[i] = 0;
+ for (k = 0; k < 2; k++)
+ pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8);
+ pDCTstat->DimmSerialNumber[i] = 0;
+ for (k = 0; k < 4; k++)
+ pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8);
+ pDCTstat->DimmRows[i] = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0xf;
+ pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_COLSZ) & 0xf;
+ pDCTstat->DimmRanks[i] = (mctRead_SPD(smbaddr, SPD_DMBANKS) & 0x7) + 1;
+ pDCTstat->DimmBanks[i] = mctRead_SPD(smbaddr, SPD_LBANKS);
+ pDCTstat->DimmWidth[i] = mctRead_SPD(smbaddr, SPD_DEVWIDTH);
+ }
/* Check module type */
byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE);
- if (byte & JED_REGADCMSK)
+ if (byte & JED_REGADCMSK) {
RegDIMMPresent |= 1 << i;
+ pDCTstat->DimmRegistered[i] = 1;
+ }
+ else {
+ pDCTstat->DimmRegistered[i] = 0;
+ }
/* Check ECC capable */
byte = mctRead_SPD(smbaddr, SPD_EDCTYPE);
if (byte & JED_ECC) {
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index 0a1f925..a200873 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -1,6 +1,7 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -231,10 +232,17 @@
#define SPD_TRC 41
#define SPD_TRFC 42
+#define SPD_MANID_START 64
+#define SPD_PARTN_START 73
+#define SPD_PARTN_LENGTH 18
+#define SPD_REVNO_START 91
+
#define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/
#define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/
+#define SPD_SERIAL_START 95
+
/*-----------------------------
Jedec DDR II related equates
-----------------------------*/
@@ -512,6 +520,18 @@ struct DCTStatStruc { /* A per Node structure*/
u32 dev_map;
u32 dev_dct;
u32 dev_nbmisc;
+
+ uint8_t DimmRows[8];
+ uint8_t DimmCols[8];
+ uint8_t DimmRanks[8];
+ uint8_t DimmBanks[8];
+ uint8_t DimmWidth[8];
+ uint8_t DimmRegistered[8];
+
+ uint64_t DimmManufacturerID[8];
+ char DimmPartNumber[8][SPD_PARTN_LENGTH];
+ uint16_t DimmRevisionNumber[8];
+ uint32_t DimmSerialNumber[8];
};
/*===============================================================================
@@ -666,6 +686,17 @@ struct DCTStatStruc { /* A per Node structure*/
xx0b = disable
yy1b = enable with DctSelIntLvAddr set to yyb */
+/*===============================================================================
+ CBMEM storage
+===============================================================================*/
+struct amdmct_memory_info {
+ struct MCTStatStruc mct_stat;
+ struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED];
+ uint16_t ecc_enabled;
+ uint16_t ecc_scrub_rate;
+};
+
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val);
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index b2cfad6..39acccf 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -570,4 +570,4 @@ static u8 mctSetNodeBoundary_D(void)
{
return 0;
}
-#endif
+#endif
\ No newline at end of file
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