[coreboot-gerrit] New patch to review for coreboot: 4b93b74 build system: normalize linker script file names
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Mar 27 16:04:44 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9107
-gerrit
commit 4b93b74d4fca947ad36a89ec9fb613629bc3cbed
Author: Patrick Georgi <pgeorgi at chromium.org>
Date: Fri Mar 27 13:50:11 2015 +0100
build system: normalize linker script file names
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere.
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.
Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner at chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
---
src/arch/riscv/id.ld | 6 +++
src/arch/riscv/id.lds | 6 ---
src/arch/x86/Makefile.inc | 12 ++---
src/arch/x86/init/ldscript_failover.lb | 74 ---------------------------
src/arch/x86/init/ldscript_failover.ld | 74 +++++++++++++++++++++++++++
src/arch/x86/lib/id.ld | 6 +++
src/arch/x86/lib/id.lds | 6 ---
src/cpu/dmp/vortex86ex/Makefile.inc | 4 +-
src/cpu/dmp/vortex86ex/biosdata.ld | 84 +++++++++++++++++++++++++++++++
src/cpu/dmp/vortex86ex/biosdata.lds | 84 -------------------------------
src/cpu/dmp/vortex86ex/biosdata_ex.ld | 35 +++++++++++++
src/cpu/dmp/vortex86ex/biosdata_ex.lds | 35 -------------
src/cpu/intel/fit/fit.ld | 6 +++
src/cpu/intel/fit/fit.lds | 6 ---
src/cpu/x86/16bit/entry16.ld | 2 +
src/cpu/x86/16bit/entry16.lds | 2 -
src/cpu/x86/16bit/reset16.ld | 16 ++++++
src/cpu/x86/16bit/reset16.lds | 16 ------
src/cpu/x86/32bit/entry32.ld | 1 +
src/cpu/x86/32bit/entry32.lds | 1 -
src/northbridge/via/vx800/Makefile.inc | 2 +-
src/northbridge/via/vx800/romstrap.ld | 26 ++++++++++
src/northbridge/via/vx800/romstrap.lds | 26 ----------
src/northbridge/via/vx900/Makefile.inc | 2 +-
src/northbridge/via/vx900/romstrap.ld | 27 ++++++++++
src/northbridge/via/vx900/romstrap.lds | 27 ----------
src/southbridge/nvidia/ck804/Makefile.inc | 2 +-
src/southbridge/nvidia/ck804/nic.c | 2 +-
src/southbridge/nvidia/ck804/romstrap.ld | 26 ++++++++++
src/southbridge/nvidia/ck804/romstrap.lds | 26 ----------
src/southbridge/nvidia/mcp55/Makefile.inc | 2 +-
src/southbridge/nvidia/mcp55/nic.c | 2 +-
src/southbridge/nvidia/mcp55/romstrap.ld | 27 ++++++++++
src/southbridge/nvidia/mcp55/romstrap.lds | 27 ----------
src/southbridge/sis/sis966/Makefile.inc | 2 +-
src/southbridge/sis/sis966/romstrap.ld | 27 ++++++++++
src/southbridge/sis/sis966/romstrap.lds | 27 ----------
src/southbridge/via/k8t890/Makefile.inc | 2 +-
src/southbridge/via/k8t890/romstrap.ld | 29 +++++++++++
src/southbridge/via/k8t890/romstrap.lds | 29 -----------
40 files changed, 408 insertions(+), 408 deletions(-)
diff --git a/src/arch/riscv/id.ld b/src/arch/riscv/id.ld
new file mode 100644
index 0000000..cfd091d
--- /dev/null
+++ b/src/arch/riscv/id.ld
@@ -0,0 +1,6 @@
+SECTIONS {
+ . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
+ .id (.): {
+ *(.id)
+ }
+}
diff --git a/src/arch/riscv/id.lds b/src/arch/riscv/id.lds
deleted file mode 100644
index cfd091d..0000000
--- a/src/arch/riscv/id.lds
+++ /dev/null
@@ -1,6 +0,0 @@
-SECTIONS {
- . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
- .id (.): {
- *(.id)
- }
-}
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 5d49abc..175a767 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -72,13 +72,13 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb
-bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds
-bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds
-bootblock_lds += $(src)/arch/x86/lib/id.lds
+bootblock_lds = $(src)/arch/x86/init/ldscript_failover.ld
+bootblock_lds += $(src)/cpu/x86/16bit/entry16.ld
+bootblock_lds += $(src)/cpu/x86/16bit/reset16.ld
+bootblock_lds += $(src)/arch/x86/lib/id.ld
bootblock_lds += $(chipset_bootblock_lds)
ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_lds += $(src)/cpu/intel/fit/fit.lds
+bootblock_lds += $(src)/cpu/intel/fit/fit.ld
endif
bootblock_inc = $(src)/arch/x86/init/prologue.inc
@@ -141,7 +141,7 @@ crt0s = $(src)/arch/x86/init/prologue.inc
ldscripts =
ldscripts += $(src)/arch/x86/init/romstage.ld
crt0s += $(src)/cpu/x86/32bit/entry32.inc
-ldscripts += $(src)/cpu/x86/32bit/entry32.lds
+ldscripts += $(src)/cpu/x86/32bit/entry32.ld
crt0s += $(src)/cpu/x86/fpu_enable.inc
ifeq ($(CONFIG_SSE),y)
diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
deleted file mode 100644
index 318f429..0000000
--- a/src/arch/x86/init/ldscript_failover.lb
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* We use ELF as output format. So that we can debug the code in some form. */
-OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
-OUTPUT_ARCH(i386)
-
-MEMORY {
- rom : ORIGIN = 0xffff0000, LENGTH = 64K
-}
-
-TARGET(binary)
-SECTIONS
-{
- /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
- * with Startup IPI message without RAM. Align .rom to next 4 byte
- * boundary anyway, so no pad byte appears between _rom and _start.
- */
- .bogus ROMLOC_MIN : {
- . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4);
- ROMLOC = .;
- } >rom = 0xff
-
- /* This section might be better named .setup */
- .rom ROMLOC : {
- _rom = .;
- ap_sipi_vector = .;
- *(.rom.text);
- *(.rom.data);
- *(.rom.data.*);
- *(.rodata.*);
- _erom = .;
- } >rom = 0xff
-
- /* Allocation reserves extra 16 bytes here. Alignment requirements
- * may cause the total size of a section to change when the start
- * address gets applied.
- */
- ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
- (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
-
- /* Post-check proper SIPI vector. */
- _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0),
- "Bad SIPI vector alignment");
- _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR),
- "Address mismatch on AP_SIPI_VECTOR");
-
- /DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- *(.iplt)
- *(.rel.*)
- *(.igot.*)
- }
-}
diff --git a/src/arch/x86/init/ldscript_failover.ld b/src/arch/x86/init/ldscript_failover.ld
new file mode 100644
index 0000000..318f429
--- /dev/null
+++ b/src/arch/x86/init/ldscript_failover.ld
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+
+MEMORY {
+ rom : ORIGIN = 0xffff0000, LENGTH = 64K
+}
+
+TARGET(binary)
+SECTIONS
+{
+ /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
+ * with Startup IPI message without RAM. Align .rom to next 4 byte
+ * boundary anyway, so no pad byte appears between _rom and _start.
+ */
+ .bogus ROMLOC_MIN : {
+ . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4);
+ ROMLOC = .;
+ } >rom = 0xff
+
+ /* This section might be better named .setup */
+ .rom ROMLOC : {
+ _rom = .;
+ ap_sipi_vector = .;
+ *(.rom.text);
+ *(.rom.data);
+ *(.rom.data.*);
+ *(.rodata.*);
+ _erom = .;
+ } >rom = 0xff
+
+ /* Allocation reserves extra 16 bytes here. Alignment requirements
+ * may cause the total size of a section to change when the start
+ * address gets applied.
+ */
+ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
+ (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
+
+ /* Post-check proper SIPI vector. */
+ _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0),
+ "Bad SIPI vector alignment");
+ _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR),
+ "Address mismatch on AP_SIPI_VECTOR");
+
+ /DISCARD/ : {
+ *(.comment)
+ *(.note)
+ *(.comment.*)
+ *(.note.*)
+ *(.iplt)
+ *(.rel.*)
+ *(.igot.*)
+ }
+}
diff --git a/src/arch/x86/lib/id.ld b/src/arch/x86/lib/id.ld
new file mode 100644
index 0000000..cfd091d
--- /dev/null
+++ b/src/arch/x86/lib/id.ld
@@ -0,0 +1,6 @@
+SECTIONS {
+ . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
+ .id (.): {
+ *(.id)
+ }
+}
diff --git a/src/arch/x86/lib/id.lds b/src/arch/x86/lib/id.lds
deleted file mode 100644
index cfd091d..0000000
--- a/src/arch/x86/lib/id.lds
+++ /dev/null
@@ -1,6 +0,0 @@
-SECTIONS {
- . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
- .id (.): {
- *(.id)
- }
-}
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index ff0b58c..c68bf9e 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -25,7 +25,7 @@ subdirs-y += ../../x86/smm
chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
-chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata.lds
-chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata_ex.lds
+chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata.ld
+chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata_ex.ld
ROMCCFLAGS := -mcpu=i386 -O2
diff --git a/src/cpu/dmp/vortex86ex/biosdata.ld b/src/cpu/dmp/vortex86ex/biosdata.ld
new file mode 100644
index 0000000..b525b2a
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/biosdata.ld
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+SECTIONS {
+
+ /* Vortex86 ROM fixed data areas used range is too big, we need
+ * to move bootblock from default address to another place,
+ * otherwise .dmp_frontdoor section can't be included.
+ * Address before ..fbc00 is available.
+ */
+ ROMLOC_MIN = 0xffffbc00 - (_erom - _rom + 16) -
+ (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
+
+ . = 0xffffbc00;
+ .dmp_reserved (.): {
+ *(.dmp_reserved)
+ }
+
+ . = 0xffffc000;
+ .dmp_kbd_fw_part2 (.): {
+ *(.dmp_kbd_fw_part2)
+ }
+
+ . = 0xffffd000;
+ .dmp_mtbf_low_cnt (.): {
+ *(.dmp_mtbf_low_cnt)
+ }
+
+ . = 0xffffe000;
+ .dmp_kbd_fw_part1 (.): {
+ *(.dmp_kbd_fw_part1)
+ }
+
+ . = 0xfffff000;
+ .dmp_spi_flash_disk_driver (.): {
+ *(.dmp_spi_flash_disk_driver)
+ }
+
+ . = 0xfffff800;
+ .dmp_frontdoor (.): {
+ *(.dmp_frontdoor)
+ }
+
+ . = 0xfffffe00;
+ .dmp_isoinfo (.): {
+ *(.dmp_isoinfo)
+ }
+
+ . = 0xffffffa0;
+ .dmp_isodata_checksum (.): {
+ *(.dmp_isodata_checksum)
+ }
+
+ . = 0xffffffb0;
+ .dmp_mac (.): {
+ *(.dmp_mac)
+ }
+
+ . = 0xffffffb8;
+ .dmp_mtbf_limit (.): {
+ *(.dmp_mtbf_limit)
+ }
+
+ . = 0xffffffc0;
+ .dmp_isodata (.): {
+ *(.dmp_isodata)
+ }
+}
diff --git a/src/cpu/dmp/vortex86ex/biosdata.lds b/src/cpu/dmp/vortex86ex/biosdata.lds
deleted file mode 100644
index b525b2a..0000000
--- a/src/cpu/dmp/vortex86ex/biosdata.lds
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-SECTIONS {
-
- /* Vortex86 ROM fixed data areas used range is too big, we need
- * to move bootblock from default address to another place,
- * otherwise .dmp_frontdoor section can't be included.
- * Address before ..fbc00 is available.
- */
- ROMLOC_MIN = 0xffffbc00 - (_erom - _rom + 16) -
- (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
-
- . = 0xffffbc00;
- .dmp_reserved (.): {
- *(.dmp_reserved)
- }
-
- . = 0xffffc000;
- .dmp_kbd_fw_part2 (.): {
- *(.dmp_kbd_fw_part2)
- }
-
- . = 0xffffd000;
- .dmp_mtbf_low_cnt (.): {
- *(.dmp_mtbf_low_cnt)
- }
-
- . = 0xffffe000;
- .dmp_kbd_fw_part1 (.): {
- *(.dmp_kbd_fw_part1)
- }
-
- . = 0xfffff000;
- .dmp_spi_flash_disk_driver (.): {
- *(.dmp_spi_flash_disk_driver)
- }
-
- . = 0xfffff800;
- .dmp_frontdoor (.): {
- *(.dmp_frontdoor)
- }
-
- . = 0xfffffe00;
- .dmp_isoinfo (.): {
- *(.dmp_isoinfo)
- }
-
- . = 0xffffffa0;
- .dmp_isodata_checksum (.): {
- *(.dmp_isodata_checksum)
- }
-
- . = 0xffffffb0;
- .dmp_mac (.): {
- *(.dmp_mac)
- }
-
- . = 0xffffffb8;
- .dmp_mtbf_limit (.): {
- *(.dmp_mtbf_limit)
- }
-
- . = 0xffffffc0;
- .dmp_isodata (.): {
- *(.dmp_isodata)
- }
-}
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.ld b/src/cpu/dmp/vortex86ex/biosdata_ex.ld
new file mode 100644
index 0000000..d711648
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/biosdata_ex.ld
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+SECTIONS {
+ . = 0xfffffd00;
+ .a9123_crossbar_config (.): {
+ *(.a9123_crossbar_config)
+ }
+
+ . = 0xffffffb6;
+ .a9123_strap_1 (.): {
+ *(.a9123_strap_1)
+ }
+
+ . = 0xffffffbb;
+ .a9123_strap_2 (.): {
+ *(.a9123_strap_2)
+ }
+}
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.lds b/src/cpu/dmp/vortex86ex/biosdata_ex.lds
deleted file mode 100644
index d711648..0000000
--- a/src/cpu/dmp/vortex86ex/biosdata_ex.lds
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-SECTIONS {
- . = 0xfffffd00;
- .a9123_crossbar_config (.): {
- *(.a9123_crossbar_config)
- }
-
- . = 0xffffffb6;
- .a9123_strap_1 (.): {
- *(.a9123_strap_1)
- }
-
- . = 0xffffffbb;
- .a9123_strap_2 (.): {
- *(.a9123_strap_2)
- }
-}
diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld
new file mode 100644
index 0000000..9ccfe82
--- /dev/null
+++ b/src/cpu/intel/fit/fit.ld
@@ -0,0 +1,6 @@
+SECTIONS {
+ . = 0xffffffc0;
+ .fit_pointer (.): {
+ *(.fit_pointer)
+ }
+}
diff --git a/src/cpu/intel/fit/fit.lds b/src/cpu/intel/fit/fit.lds
deleted file mode 100644
index 9ccfe82..0000000
--- a/src/cpu/intel/fit/fit.lds
+++ /dev/null
@@ -1,6 +0,0 @@
-SECTIONS {
- . = 0xffffffc0;
- .fit_pointer (.): {
- *(.fit_pointer)
- }
-}
diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld
new file mode 100644
index 0000000..112d429
--- /dev/null
+++ b/src/cpu/x86/16bit/entry16.ld
@@ -0,0 +1,2 @@
+ gdtptr16_offset = gdtptr16 & 0xffff;
+ nullidt_offset = nullidt & 0xffff;
diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.lds
deleted file mode 100644
index 112d429..0000000
--- a/src/cpu/x86/16bit/entry16.lds
+++ /dev/null
@@ -1,2 +0,0 @@
- gdtptr16_offset = gdtptr16 & 0xffff;
- nullidt_offset = nullidt & 0xffff;
diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld
new file mode 100644
index 0000000..a31a580
--- /dev/null
+++ b/src/cpu/x86/16bit/reset16.ld
@@ -0,0 +1,16 @@
+/*
+ * _ROMTOP : The top of the rom used where we
+ * need to put the reset vector.
+ */
+
+SECTIONS {
+ /* Trigger an error if I have an unuseable start address */
+ _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please report.");
+ _ROMTOP = 0xfffffff0;
+ . = _ROMTOP;
+ .reset . : {
+ *(.reset)
+ . = 15 ;
+ BYTE(0x00);
+ }
+}
diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds
deleted file mode 100644
index a31a580..0000000
--- a/src/cpu/x86/16bit/reset16.lds
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * _ROMTOP : The top of the rom used where we
- * need to put the reset vector.
- */
-
-SECTIONS {
- /* Trigger an error if I have an unuseable start address */
- _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please report.");
- _ROMTOP = 0xfffffff0;
- . = _ROMTOP;
- .reset . : {
- *(.reset)
- . = 15 ;
- BYTE(0x00);
- }
-}
diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld
new file mode 100644
index 0000000..471b5f7
--- /dev/null
+++ b/src/cpu/x86/32bit/entry32.ld
@@ -0,0 +1 @@
+ENTRY(protected_start)
diff --git a/src/cpu/x86/32bit/entry32.lds b/src/cpu/x86/32bit/entry32.lds
deleted file mode 100644
index 471b5f7..0000000
--- a/src/cpu/x86/32bit/entry32.lds
+++ /dev/null
@@ -1 +0,0 @@
-ENTRY(protected_start)
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 39ebdbd..1963880 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -24,4 +24,4 @@ ramstage-y += lpc.c
ramstage-y += ide.c
chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
-chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.lds
+chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.ld
diff --git a/src/northbridge/via/vx800/romstrap.ld b/src/northbridge/via/vx800/romstrap.ld
new file mode 100644
index 0000000..8aa570f
--- /dev/null
+++ b/src/northbridge/via/vx800/romstrap.ld
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * (Written by Yinghai Lu <yinghai.lu at amd.com> for AMD)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+SECTIONS {
+ . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1;
+ .romstrap (.): {
+ *(.romstrap)
+ }
+}
diff --git a/src/northbridge/via/vx800/romstrap.lds b/src/northbridge/via/vx800/romstrap.lds
deleted file mode 100644
index 8aa570f..0000000
--- a/src/northbridge/via/vx800/romstrap.lds
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghai.lu at amd.com> for AMD)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-SECTIONS {
- . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1;
- .romstrap (.): {
- *(.romstrap)
- }
-}
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 15fd859..85282dd 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -45,4 +45,4 @@ ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
-chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds
+chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.ld
diff --git a/src/northbridge/via/vx900/romstrap.ld b/src/northbridge/via/vx900/romstrap.ld
new file mode 100644
index 0000000..fc63c05
--- /dev/null
+++ b/src/northbridge/via/vx900/romstrap.ld
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * (Written by Yinghai Lu <yinghai.lu at amd.com> for AMD)
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>
+ */
+
+SECTIONS {
+ . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start);
+ .romstrap (.): {
+ *(.romstrap)
+ }
+}
diff --git a/src/northbridge/via/vx900/romstrap.lds b/src/northbridge/via/vx900/romstrap.lds
deleted file mode 100644
index fc63c05..0000000
--- a/src/northbridge/via/vx900/romstrap.lds
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghai.lu at amd.com> for AMD)
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>
- */
-
-SECTIONS {
- . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start);
- .romstrap (.): {
- *(.romstrap)
- }
-}
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index db145d0..dacfc9c 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -20,4 +20,4 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_smbus.c
chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
-chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds
+chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.ld
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index b827dcf..1207a95 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -90,7 +90,7 @@ static void nic_init(struct device *dev)
/* If that is invalid we will read that from romstrap. */
if (!eeprom_valid) {
u32 *mac_pos;
- mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */
+ mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.ld. */
mac_l = read32(mac_pos) + nic_index;
mac_h = read32(mac_pos + 1);
}
diff --git a/src/southbridge/nvidia/ck804/romstrap.ld b/src/southbridge/nvidia/ck804/romstrap.ld
new file mode 100644
index 0000000..4d7996f
--- /dev/null
+++ b/src/southbridge/nvidia/ck804/romstrap.ld
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+SECTIONS {
+ . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1;
+ .romstrap (.): {
+ *(.romstrap)
+ }
+}
diff --git a/src/southbridge/nvidia/ck804/romstrap.lds b/src/southbridge/nvidia/ck804/romstrap.lds
deleted file mode 100644
index 4d7996f..0000000
--- a/src/southbridge/nvidia/ck804/romstrap.lds
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-SECTIONS {
- . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1;
- .romstrap (.): {
- *(.romstrap)
- }
-}
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index 03a34eb..b4dc460 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -19,4 +19,4 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
-chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds
+chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.ld
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index 136d060..d8f691a 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -162,7 +162,7 @@ static void nic_init(struct device *dev)
// if that is invalid we will read that from romstrap
if(!eeprom_valid) {
u32 *mac_pos;
- mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.lds
+ mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld
mac_l = read32(mac_pos) + nic_index; // overflow?
mac_h = read32(mac_pos + 1);
diff --git a/src/southbridge/nvidia/mcp55/romstrap.ld b/src/southbridge/nvidia/mcp55/romstrap.ld
new file mode 100644
index 0000000..784e7d5
--- /dev/null
+++ b/src/southbridge/nvidia/mcp55/romstrap.ld
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+SECTIONS {
+ . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1;
+ .romstrap (.): {
+ *(.romstrap)
+ }
+}
diff --git a/src/southbridge/nvidia/mcp55/romstrap.lds b/src/southbridge/nvidia/mcp55/romstrap.lds
deleted file mode 100644
index 784e7d5..0000000
--- a/src/southbridge/nvidia/mcp55/romstrap.lds
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-SECTIONS {
- . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1;
- .romstrap (.): {
- *(.romstrap)
- }
-}
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 1a9ea65..5c69622 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -14,4 +14,4 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
-chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds
+chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.ld
diff --git a/src/southbridge/sis/sis966/romstrap.ld b/src/southbridge/sis/sis966/romstrap.ld
new file mode 100644
index 0000000..784e7d5
--- /dev/null
+++ b/src/southbridge/sis/sis966/romstrap.ld
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+SECTIONS {
+ . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1;
+ .romstrap (.): {
+ *(.romstrap)
+ }
+}
diff --git a/src/southbridge/sis/sis966/romstrap.lds b/src/southbridge/sis/sis966/romstrap.lds
deleted file mode 100644
index 784e7d5..0000000
--- a/src/southbridge/sis/sis966/romstrap.lds
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-SECTIONS {
- . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1;
- .romstrap (.): {
- *(.romstrap)
- }
-}
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 6d9407d..1c5ff3f 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -9,4 +9,4 @@ ramstage-y += error.c
ramstage-y += chrome.c
chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
-chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds
+chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.ld
diff --git a/src/southbridge/via/k8t890/romstrap.ld b/src/southbridge/via/k8t890/romstrap.ld
new file mode 100644
index 0000000..235769d
--- /dev/null
+++ b/src/southbridge/via/k8t890/romstrap.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * (Written by Yinghai Lu <yinghai.lu at amd.com> for AMD)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek at assembler.cz>. */
+
+SECTIONS {
+ . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1;
+ .romstrap (.): {
+ *(.romstrap)
+ }
+}
diff --git a/src/southbridge/via/k8t890/romstrap.lds b/src/southbridge/via/k8t890/romstrap.lds
deleted file mode 100644
index 235769d..0000000
--- a/src/southbridge/via/k8t890/romstrap.lds
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghai.lu at amd.com> for AMD)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek at assembler.cz>. */
-
-SECTIONS {
- . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1;
- .romstrap (.): {
- *(.romstrap)
- }
-}
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