[coreboot-gerrit] Patch set updated for coreboot: 37ed3c0 arm64: initialize secmon environment

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9091

-gerrit

commit 37ed3c069e0607916e9ca9bedeef43fa3f9e7314
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Sep 18 14:23:59 2014 -0500

    arm64: initialize secmon environment
    
    The exception vectors were not reinitialized in secmon yet.
    Add that as well as the split BSP vs non-BSP path. In doing
    so bring in the cpu.c semantics for determining bsp at runtime.
    
    BUG=chrome-os-partner:30785
    BRANCH=None
    TEST=Built and booted to kernel. Also noted only one CPU
         printing messages.
    
    Change-Id: I26a7f9446f4422d2203b1d520e69f8dee9450b59
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 67f79c61c902ee614f029047255b4be35112cd32
    Original-Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/218845
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
 src/arch/arm64/armv8/secmon/Makefile.inc  |  2 ++
 src/arch/arm64/armv8/secmon/secmon_init.c | 45 ++++++++++++++++++++-----------
 src/arch/arm64/armv8/secmon_loader.c      | 16 ++++++++---
 3 files changed, 43 insertions(+), 20 deletions(-)

diff --git a/src/arch/arm64/armv8/secmon/Makefile.inc b/src/arch/arm64/armv8/secmon/Makefile.inc
index b140941..5dadfa9 100644
--- a/src/arch/arm64/armv8/secmon/Makefile.inc
+++ b/src/arch/arm64/armv8/secmon/Makefile.inc
@@ -32,6 +32,8 @@ secmon-c-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kc
 secmon-S-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h -D__SECMON__
 
 secmon-y += secmon_init.c
+secmon-y += ../exception.c
+secmon-y += ../../cpu.c
 secmon-y += ../../transition_asm.S ../../transition.c
 
 ramstage-srcs += $(SECMON_SRC)
diff --git a/src/arch/arm64/armv8/secmon/secmon_init.c b/src/arch/arm64/armv8/secmon/secmon_init.c
index e8bdd82..660d6d4 100644
--- a/src/arch/arm64/armv8/secmon/secmon_init.c
+++ b/src/arch/arm64/armv8/secmon/secmon_init.c
@@ -21,6 +21,7 @@
 
 #include <arch/barrier.h>
 #include <arch/io.h>
+#include <arch/exception.h>
 #include <arch/lib_helpers.h>
 #include <arch/secmon.h>
 #include <arch/transition.h>
@@ -28,14 +29,15 @@
 #include <rmodule.h>
 #include <stddef.h>
 
-static void secmon_wait(void)
+static void cpu_init(int bsp)
 {
-	/*
-	 * TODO(furquan): This should be a point of no-return. Once we have PSCI
-	 * support we need to respond to kernel calls
-	 */
-	while (1)
-		wfe();
+	struct cpu_info *ci = cpu_info();
+
+	ci->id = smp_processor_id();
+	cpu_mark_online(ci);
+
+	if (bsp)
+		cpu_set_bsp();
 }
 
 static void secmon_el3_init(void)
@@ -52,12 +54,12 @@ static void secmon_el3_init(void)
 	isb();
 }
 
-static void secmon_init(void *arg)
+static void secmon_init(struct secmon_params *params, int bsp)
 {
 	struct exc_state exc_state;
-	struct secmon_params *params = arg;
 
-	printk(BIOS_DEBUG, "ARM64: secmon in %s\n", __func__);
+	exception_hwinit();
+	cpu_init(bsp);
 
 	secmon_el3_init();
 
@@ -66,18 +68,29 @@ static void secmon_init(void *arg)
 	 * 1) If yes, we make an EL2 transition to that entry point
 	 * 2) If no, we just wait
 	 */
-	if (params == NULL) {
-		secmon_wait();
+	if (params != NULL) {
+		memset(&exc_state, 0, sizeof(exc_state));
+		exc_state.elx.spsr =
+			get_eret_el(params->elx_el, params->elx_mode);
+
+		transition_with_entry(params->entry, params->arg, &exc_state);
 	}
 
-	memset(&exc_state, 0, sizeof(exc_state));
-	exc_state.elx.spsr = get_eret_el(params->elx_el, params->elx_mode);
+	arch_cpu_wait_for_action();
+}
 
-	transition_with_entry(params->entry, params->arg, &exc_state);
+static void secmon_init_bsp(void *arg)
+{
+	secmon_init(arg, 1);
+}
+
+static void secmon_init_nonbsp(void *arg)
+{
+	secmon_init(arg, 0);
 }
 
 /*
  * This variable holds entry point for secmon init code. Once the stacks are
  * setup by the stage_entry.S, it jumps to c_entry.
  */
-void (*c_entry)(void*) = &secmon_init;
+void (*c_entry[2])(void*) = { &secmon_init_bsp, &secmon_init_nonbsp };
diff --git a/src/arch/arm64/armv8/secmon_loader.c b/src/arch/arm64/armv8/secmon_loader.c
index 4d83764..e571b51 100644
--- a/src/arch/arm64/armv8/secmon_loader.c
+++ b/src/arch/arm64/armv8/secmon_loader.c
@@ -25,6 +25,7 @@
 #include <arch/lib_helpers.h>
 #include <arch/secmon.h>
 #include <arch/spintable.h>
+#include <arch/stages.h>
 #include <console/console.h>
 #include <rmodule.h>
 #include <string.h>
@@ -85,15 +86,22 @@ struct secmon_runit {
 static void secmon_start(void *arg)
 {
 	uint32_t scr;
+	secmon_entry_t entry;
 	struct secmon_params *p = NULL;
 	struct secmon_runit *r = arg;
 
+	entry = r->entry;
+
 	if (cpu_is_bsp())
 		p = &r->bsp_params;
-	else if (r->secondary_params.entry != NULL)
-		p = &r->secondary_params;
+	else {
+		entry = secondary_entry_point(entry);
+		if (r->secondary_params.entry != NULL)
+			p = &r->secondary_params;
+	}
 
-	printk(BIOS_DEBUG, "CPU%x entering secure monitor.\n", cpu_info()->id);
+	printk(BIOS_DEBUG, "CPU%x entering secure monitor %p.\n",
+		cpu_info()->id, entry);
 
 	/* We want to enforce the following policies:
 	 * NS bit is set for lower EL
@@ -102,7 +110,7 @@ static void secmon_start(void *arg)
 	scr |= SCR_NS;
 	raw_write_scr_el3(scr);
 
-	r->entry(p);
+	entry(p);
 }
 
 void secmon_run(void (*entry)(void *), void *cb_tables)