[coreboot-gerrit] Patch merged into coreboot/master: 49aad6b soc/imgtec/pistachio: Add IMGTEC SPI controller driver

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 49aad6b387b3885f43d75aa50eceab50c6ac4aa9
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Tue Sep 9 20:18:55 2014 +0100

    soc/imgtec/pistachio: Add IMGTEC SPI controller driver
    
    The Serial Peripheral Flash Interface (SPFI) block allows
    communication with various devices over the SPI bus.
    
    It uses a configurable transaction interface and it clocks
    the bus according to the configured command, address, gap (aka
    dummy) and data lengths.
    
    This controller requires the SPI_ATOMIC_SEQUENCING flag set
    (write and read done in the same transaction) as it cannot
    directly control CS and will assert/de-assert CS at the
    beginning/end of a transaction itself.
    
    Note that the size of any transfer cannot be greater than
    64KB - 1, as this is configured in a 16-bit field.
    
    The SOC has 2 SPFI interfaces each of them providing 5 slave select
    lines. SPFI 0 supports single and dual modes, SPFI 1 supports
    single, dual and quad modes.
    
    For SPFI interface 0:
     - The block needs the system PLL and the following top level
       SPI clock registers to be set:
       - CR_cr_top_spi0clkinternal_CTRL[2:0] with division value
       - CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set
       - CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value
     - The following MFIO configuration parameters are also required:
       Signal name		Pad name        MFIO mode
       spim0_d0_txd		MFIO_MIPS_10	0
       spim0_d1_rxd		MFIO_MIPS_9	0
       spim0_mclk		MFIO_MIPS_8	0
       spim0_cs0		MFIO_MIPS_2	1
       spim0_cs1		MFIO_MIPS_1	1
       spim0_cs2		MFIO_MIPS_55	1
    			MFIO_MIPS_28	1
       spim0_cs3		MFIO_MIPS_56	1
    			MFIO_MIPS_29	1
       spim0_cs4		MFIO_MIPS_57	1
    			MFIO_MIMPS_30	1
    
    For SPFI interface 1:
     - The block needs the system PLL and the following top level
       SPI clock registers to be set:
       - CR_cr_top_spi1clkinternal_CTRL[2:0] with division value
       - CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set
       - CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value
     - The following MFIO configuration parameters are also required:
       Signal name		Pad name	MFIO mode
       spim1_d0_txd		MFIO_MIPS_5	0
       spim1_d1_rxd		MFIO_MIPS_4	0
       spim1_mclk		MFIO_MIPS_3	0
       spim1_d2		MFIO_MIPS_6	0
       spim1_d3		MFIO_MIPS_7	0
       spim1_cs0		MFIO_MIPS_0	0
       spim1_cs1		MFIO_MIPS_1	0
       			MFIO_MIPS_58	1
       spim1_cs2		MFIO_MIPS_2	0
       			MFIO_MIPS_55	2
       			MFIO_MIPS_31	1
       spim1_cs3		MFIO_MIPS_56	2
       spim1_cs4		MFIO_MIPS_57	2
    
    BUG=chrome-os-partner:31438, chrome-os-partner:32441
    TEST=Tested as bare-metal driver on Pistachio FPGA
    
    Change-Id: I3b3e4475976e6fba58cef93b12d997ec5cb26341
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 621849942e27f7d6cf2c8ade7f2c4d18d2318b91
    Original-Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/217320
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: http://review.coreboot.org/9049
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9049 for details.

-gerrit