[coreboot-gerrit] Patch set updated for coreboot: 692afd7 broadwell: Apply pcie updates from 2.1.0 ref code

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8967

-gerrit

commit 692afd7bdbce1b7365226bf505c71d1919a6a110
Author: Kane Chen <kane.chen at intel.com>
Date:   Wed Aug 27 15:21:32 2014 -0700

    broadwell: Apply pcie updates from 2.1.0 ref code
    
    some clock gating and pcie settings are missed in original code
    
    BUG=chrome-os-partner:28234
    BRANCH=None
    TEST=build and boot on samus
         verify registers between samus and crb
    
    Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492
    Original-Signed-off-by: Kane Chen <kane.chen at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/214568
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    (cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093
---
 src/soc/intel/broadwell/pcie.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index a251a17..bd5dc3c 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -31,6 +31,7 @@
 #include <broadwell/pci_devs.h>
 #include <broadwell/rcba.h>
 #include <chip.h>
+#include <broadwell/cpu.h>
 
 static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
 static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
@@ -107,6 +108,7 @@ static void root_port_init_config(device_t dev)
 		rpc.new_rpfn = rpc.orig_rpfn;
 		rpc.num_ports = NUM_ROOT_PORTS;
 		rpc.gbe_port = -1;
+		pcie_update_cfg8(dev, 0xf5, 0xa, 0x5);
 
 		rpc.pin_ownership = pci_read_config32(dev, 0x410);
 		root_port_config_update_gbe_port();
@@ -176,6 +178,7 @@ static void pcie_enable_clock_gating(void)
 {
 	int i;
 	int enabled_ports = 0;
+	int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
 
 	for (i = 0; i < rpc.num_ports; i++) {
 		device_t dev;
@@ -216,9 +219,13 @@ static void pcie_enable_clock_gating(void)
 		pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2));
 
 		/* Update PECR1 register. */
-		pcie_update_cfg8(dev, 0xe8, ~0, 1);
-		pcie_update_cfg8(dev, 0x324, ~(1 << 5), (1 < 5));
-
+		pcie_update_cfg8(dev, 0xe8, ~0, 3);
+		if (is_broadwell) {
+			pcie_update_cfg(dev, 0x324, ~((1 << 5) | (1 << 14)),
+					((1 << 5) | (1 << 14)));
+		} else {
+			pcie_update_cfg(dev, 0x324, ~(1 << 5), (1 << 5));
+		}
 		/* Per-Port CLKREQ# handling. */
 		if (gpio_is_native(18 + rp - 1))
 			pcie_update_cfg(dev, 0x420, ~0, (3 << 29));
@@ -455,9 +462,6 @@ static void pch_pcie_early(struct device *dev)
 		/* Set unique clock exit latency in MPC register. */
 		pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
 
-		/* Set L1 exit latency in LCAP register. */
-		pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
-
 		switch (rp) {
 		case 1:
 			pcie_add_0x0202000_iobp(0xe9002440);
@@ -515,7 +519,7 @@ static void pch_pcie_early(struct device *dev)
 	/* Set Invalid Receive Range Check Enable in MPC register. */
 	pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));
 
-	pcie_update_cfg8(dev, 0xf5, 0x3f, 0);
+	pcie_update_cfg8(dev, 0xf5, 0x0f, 0);
 
 	if (rp == 1 || rp == 5 || rp == 6)
 		pcie_update_cfg8(dev, 0xf7, ~0xc, 0);