[coreboot-gerrit] Patch merged into coreboot/master: 1b0d5a3 broadwell: Fix devslp enable to use correct register

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 1b0d5a3c17d4d17cf35f83ec0b0e9a8cae125909
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Aug 13 16:59:34 2014 -0700

    broadwell: Fix devslp enable to use correct register
    
    This was a merge error when I was pulling in some of the
    code into this file I put it after the read of CAP2 but
    before it is modified and written back.  In the end the
    DEVSLP bits are getting set/cleared that need to but the
    other bits in the register may be wrong.  Also when enabling
    devslp set the devslp-present bit in each enabled port.
    
    Also remove much of the 0:1f.2 at 0x98 setup and the attempt
    to write (the write once) CAP register that is already
    being written in the reference code.
    
    BUG=chrome-os-partner:28234
    BRANCH=None
    TEST=build and boot on samus
    
    Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/212308
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77
    Reviewed-on: http://review.coreboot.org/8958
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at google.com>


See http://review.coreboot.org/8958 for details.

-gerrit