[coreboot-gerrit] New patch to review for coreboot: a29df63 dmp/vortex86: move PLL config to cpu Kconfig
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Fri Mar 27 05:36:27 CET 2015
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9058
-gerrit
commit a29df6339e8f67f1e1bedac3d11dd43f51d3ea30
Author: Martin Roth <gaumless at gmail.com>
Date: Thu Mar 26 22:33:31 2015 -0600
dmp/vortex86: move PLL config to cpu Kconfig
I noticed that the dmp/vortex86ex mainboard kconfig was creating over
300 #defines in config.h, so I'm working to clean it up and reduce the
number of defines.
This moves the cpu's pll configuration into the cpu's Kconfig, and
reduces the number of kconfig #defines by 12. It isn't nearly as
nice looking though.
Change-Id: I72ee1baa3a96586fceff03ff43c5f61e2498667e
Signed-off-by: Martin Roth <gaumless at gmail.com>
---
src/cpu/dmp/vortex86ex/Kconfig | 20 +++++++++++++++
src/cpu/dmp/vortex86ex/biosdata.h | 30 ++++++++++++++++++++++
src/cpu/dmp/vortex86ex/biosdata_ex.inc | 30 +++++++++++-----------
src/mainboard/dmp/vortex86ex/Kconfig | 46 ----------------------------------
4 files changed, 66 insertions(+), 60 deletions(-)
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
index 080bb64..e867f5a 100644
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -24,3 +24,23 @@ config CPU_DMP_VORTEX86EX
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select UDELAY_TSC
+
+# ROM Strap PLL config setting
+config VORTEX_PLL
+ hex "ROM Strap PLL config (see help for values)"
+ default 0x01
+ help
+ 0x00 = CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz
+ 0x01 = CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz
+ 0x02 = CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz
+ 0x03 = CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz
+ 0x04 = CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz
+ 0x05 = CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz
+ 0x06 = CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz
+ 0x07 = CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz
+ 0x08 = CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz
+ 0x09 = CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz
+ 0x0a = CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz
+ 0x0b = CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz
+ 0x0c = CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz
+
diff --git a/src/cpu/dmp/vortex86ex/biosdata.h b/src/cpu/dmp/vortex86ex/biosdata.h
new file mode 100644
index 0000000..2ddf846
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/biosdata.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define PLL_200_200_33 0x00
+#define PLL_300_300_33 0x01
+#define PLL_300_300_100 0x02
+#define PLL_400_200_33 0x03
+#define PLL_400_200_100 0x04
+#define PLL_400_400_33 0x05
+#define PLL_500_250_33 0x06
+#define PLL_500_500_33 0x07
+#define PLL_400_300_33 0x08
+#define PLL_400_300_100 0x09
+#define PLL_444_333_33 0x0a
+#define PLL_466_350_33 0x0b
+#define PLL_500_375_33 0x0c
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc
index 4a2478e..fecd621 100644
--- a/src/cpu/dmp/vortex86ex/biosdata_ex.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata_ex.inc
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include "config.h"
+#include "biosdata.h"
/*
PLL Freq = 25 * NS /(MS * 2^RS)
@@ -44,7 +44,9 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
500/375/33 B4 53 0F 02 AF 09
*/
-#if CONFIG_PLL_200_200_33
+
+
+#if CONFIG_VORTEX_PLL == PLL_200_200_33
// 200/200/33 30 03 0F 02 8F 07
byte_fffb6 = 0x30
byte_fffb7 = 0x03
@@ -52,7 +54,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_300_300_33
+#elif CONFIG_VORTEX_PLL == PLL_300_300_33
// 300/300/33 48 03 0F 02 1F 07
byte_fffb6 = 0x48
byte_fffb7 = 0x03
@@ -60,7 +62,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_300_300_100
+#elif CONFIG_VORTEX_PLL == PLL_300_300_100
// 300/300/100 48 03 23 02 7F 07
byte_fffb6 = 0x48
byte_fffb7 = 0x03
@@ -68,7 +70,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_400_200_33
+#elif CONFIG_VORTEX_PLL == PLL_400_200_33
// 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing
byte_fffb6 = 0x60
byte_fffb7 = 0x43
@@ -76,7 +78,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_400_200_100
+#elif CONFIG_VORTEX_PLL == PLL_400_200_100
// 400/200/100 60 43 23 02 4F 07
byte_fffb6 = 0x60
byte_fffb7 = 0x43
@@ -84,7 +86,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_400_400_33
+#elif CONFIG_VORTEX_PLL == PLL_400_400_33
// 400/400/33 60 03 0F 02 BF 09
byte_fffb6 = 0x60
byte_fffb7 = 0x03
@@ -92,7 +94,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x09
-#elif CONFIG_PLL_500_250_33
+#elif CONFIG_VORTEX_PLL == PLL_500_250_33
// 500/250/33 50 42 0F 02 DF 07
byte_fffb6 = 0x50
byte_fffb7 = 0x42
@@ -100,7 +102,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_500_500_33
+#elif CONFIG_VORTEX_PLL == PLL_500_500_33
// 500/500/33 78 03 0F 02 4F 09
byte_fffb6 = 0x78
byte_fffb7 = 0x03
@@ -108,7 +110,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x09
-#elif CONFIG_PLL_400_300_33
+#elif CONFIG_VORTEX_PLL == PLL_400_300_33
// 400/300/33 90 53 0F 02 3F 07
byte_fffb6 = 0x90
byte_fffb7 = 0x53
@@ -116,7 +118,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_400_300_100
+#elif CONFIG_VORTEX_PLL == PLL_400_300_100
// 400/300/100 90 53 23 02 9F 07
byte_fffb6 = 0x90
byte_fffb7 = 0x53
@@ -124,7 +126,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_444_333_33
+#elif CONFIG_VORTEX_PLL == PLL_444_333_33
// 444/333/33 A0 53 0F 02 5F 08
byte_fffb6 = 0xa0
byte_fffb7 = 0x53
@@ -132,7 +134,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x08
-#elif CONFIG_PLL_466_350_33
+#elif CONFIG_VORTEX_PLL == PLL_466_350_33
// 466/350/33 A8 53 0F 02 DF 09
byte_fffb6 = 0xa8
byte_fffb7 = 0x53
@@ -140,7 +142,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x09
-#elif CONFIG_PLL_500_375_33
+#elif CONFIG_VORTEX_PLL == PLL_500_375_33
// 500/375/33 B4 53 0F 02 AF 09
byte_fffb6 = 0xb4
byte_fffb7 = 0x53
diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig
index d76799e..6d158e9 100644
--- a/src/mainboard/dmp/vortex86ex/Kconfig
+++ b/src/mainboard/dmp/vortex86ex/Kconfig
@@ -53,52 +53,6 @@ config I2C_BASE
hex
default 0xfb00
-# ROM Strap PLL config setting :
-
-choice
- prompt "ROM Strap PLL config"
- default PLL_300_300_33
-
-config PLL_200_200_33
- bool "CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz"
-
-config PLL_300_300_33
- bool "CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz"
-
-config PLL_300_300_100
- bool "CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz"
-
-config PLL_400_200_33
- bool "CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz"
-
-config PLL_400_200_100
- bool "CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz"
-
-config PLL_400_400_33
- bool "CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz"
-
-config PLL_500_250_33
- bool "CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz"
-
-config PLL_500_500_33
- bool "CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz"
-
-config PLL_400_300_33
- bool "CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz"
-
-config PLL_400_300_100
- bool "CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz"
-
-config PLL_444_333_33
- bool "CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz"
-
-config PLL_466_350_33
- bool "CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz"
-
-config PLL_500_375_33
- bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz"
-
-endchoice
menu "On-Chip Device Power Down Control"
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