[coreboot-gerrit] Patch set updated for coreboot: 29c1479 tegra132: return actual plld frequency

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9025

-gerrit

commit 29c1479465a02d82883b799ad8f7e20c91779657
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Aug 29 09:14:25 2014 -0500

    tegra132: return actual plld frequency
    
    Depending on the requested frequency the plld cannot
    necessarily obtain the exact clock. Therefore provide the
    closest configured frequency as a return value. This is
    equivalent to the t124 patch.
    
    BUG=chrome-os-partner:31640
    BRANCH=None
    TEST=Built and noted plld actual value close to requested.
    
    Change-Id: I9aaba81222fb97d9fbbb4156af3a7476ba654c10
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fc928db8197b465220e53b4d0ba5896b3c06a863
    Original-Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/214843
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
---
 src/soc/nvidia/tegra132/clock.c             | 26 +++++++++++++++++---------
 src/soc/nvidia/tegra132/include/soc/clock.h |  2 +-
 2 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index caeb24a..6640505 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -298,8 +298,14 @@ static void graphics_pll(void)
 	 */
 }
 
-/* Init PLLD clock source. */
-int
+/*
+ * Init PLLD clock source.
+ *
+ * @frequency: the requested plld frequency
+ *
+ * Return the plld frequency if success, otherwise return 0.
+ */
+u32
 clock_display(u32 frequency)
 {
 	/**
@@ -318,7 +324,7 @@ clock_display(u32 frequency)
 	 */
 	struct pllpad_dividers plld = { 0 };
 	u32 ref = clock_get_pll_input_khz() * 1000, m, n, p = 0;
-	u32 cf, vco;
+	u32 cf, vco, rounded_rate = frequency;
 	u32 diff, best_diff;
 	const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3,
 		  mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz,
@@ -330,7 +336,7 @@ clock_display(u32 frequency)
 	if (vco < min_vco || vco > max_vco) {
 		printk(BIOS_ERR, "%s: Cannot find out a supported VCO"
 			" for Frequency (%u).\n", __func__, frequency);
-		return -1;
+		return 0;
 	}
 
 	plld.p = p;
@@ -370,18 +376,20 @@ clock_display(u32 frequency)
 	else
 		plld.cpcon = 12;
 
-	if (best_diff)
-		printk(BIOS_ERR, "%s: Failed to match output frequency %u, "
+	if (best_diff) {
+		printk(BIOS_WARNING, "%s: Failed to match output frequency %u, "
 		       "best difference is %u.\n", __func__, frequency,
 		       best_diff);
+		rounded_rate = (ref / plld.m * plld.n) >> plld.p;
+	}
 
 	printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
-	       __func__, (ref / plld.m * plld.n) >> plld.p, ref, plld.m, plld.n,
-	       plld.p, plld.cpcon);
+	       __func__, rounded_rate, ref, plld.m, plld.n, plld.p, plld.cpcon);
 
 	init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, plld,
 		 (PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE));
-	return 0;
+
+	return rounded_rate;
 }
 
 /* Initialize the UART and put it on CLK_M so we can use it during clock_init().
diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h
index eecb735..711741b 100644
--- a/src/soc/nvidia/tegra132/include/soc/clock.h
+++ b/src/soc/nvidia/tegra132/include/soc/clock.h
@@ -285,7 +285,7 @@ enum clock_source {  /* Careful: Not true for all sources, always check TRM! */
 
 int clock_get_osc_khz(void);
 int clock_get_pll_input_khz(void);
-int clock_display(u32 frequency);
+u32 clock_display(u32 frequency);
 void clock_early_uart(void);
 void clock_external_output(int clk_id);
 void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,