[coreboot-gerrit] New patch to review for coreboot: 041c368 arm64: Initialize exception stack

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8999

-gerrit

commit 041c368b5d808eb906f2dc11cd77583ea81e6c0f
Author: Furquan Shaikh <furquan at google.com>
Date:   Thu Aug 21 12:52:06 2014 -0700

    arm64: Initialize exception stack
    
    Initialize the exception stack on stage_entry
    
    BUG=chrome-os-partner:31515
    BRANCH=None
    TEST=Exception handling works fine
    
    Change-Id: I66b4e73e77ad746e891cb2ae6662fbf0531f9d8a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a21d0a432e1742fd8b36b3f8fc7748152f7d74d2
    Original-Change-Id: I0b6fb95c660c68fb47a30e905acb910b0e2eafea
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/213673
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
 src/arch/arm64/stage_entry.S | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index c18c9cf..4c26f65 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -55,6 +55,16 @@ ENTRY(arm64_el3_startup)
 	and     x0, x0, x1
 	msr     SCR_EL3, x0
 
+	/* Initialize SP_EL3 as exception stack */
+	ldr	x0, .exception_stack_top
+	cmp	x0, #0
+	b.eq	2f
+	msr	SPSel, #1
+	isb
+
+	mov	sp, x0
+
+	2:
 	/* Have stack pointer use SP_EL0. */
 	msr	SPSel, #0
 	isb
@@ -81,6 +91,8 @@ ENTRY(arm64_el3_startup)
 	 * to the Kconfig option for cpu0. However, this code can be relocated
 	 * and reused to start up secondary cpus.
 	 */
+	.exception_stack_top:
+		.quad CONFIG_EXCEPTION_STACK_TOP
 	.stack_top:
 		.quad _estack
 	.entry: