[coreboot-gerrit] Patch set updated for coreboot: 2e77973 rush: Convert rush initialization to use funitcfg api
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Wed Mar 25 17:26:37 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8922
-gerrit
commit 2e7797372553846b01f90b25c6fcc31c01205b11
Author: Furquan Shaikh <furquan at google.com>
Date: Sat Aug 9 02:04:39 2014 -0700
rush: Convert rush initialization to use funitcfg api
Use funitcfg api for bootblock, romstage as well as ramstage
initialization in rush.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully and boots till last known good point.
Change-Id: I243597de9ec13904a2bb58a04b402f9545424760
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 0618ea6828bae3e700b85b79b185aec28568b8ae
Original-Change-Id: I8f5801c1c214f05ef9d2ba976838605da2d8b914
Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211766
Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
src/mainboard/google/rush/bootblock.c | 23 +++++++++++++----------
src/mainboard/google/rush/mainboard.c | 23 ++++++++++-------------
src/mainboard/google/rush/romstage.c | 26 ++++++++++++--------------
3 files changed, 35 insertions(+), 37 deletions(-)
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c
index 17372bd..6b81a8b 100644
--- a/src/mainboard/google/rush/bootblock.c
+++ b/src/mainboard/google/rush/bootblock.c
@@ -24,6 +24,7 @@
#include <soc/bootblock.h>
#include <soc/clock.h>
#include <soc/padconfig.h>
+#include <soc/funitcfg.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra132/clk_rst.h>
#include <soc/nvidia/tegra132/spi.h> /* FIXME: move back to soc code? */
@@ -51,9 +52,15 @@ static const struct pad_config padcfgs[] = {
PAD_CFG_GPIO_INPUT(GPIO_X1_AUD, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_ROW17, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
+};
+
+static const struct pad_config i2cpad[] = {
/* PMIC i2C bus */
PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
+};
+
+static const struct pad_config spipad[] = {
/* SPI fLash: mosi, miso, clk, cs0 */
PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
@@ -61,6 +68,11 @@ static const struct pad_config padcfgs[] = {
PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4),
};
+static const struct funit_cfg funitcfgs[] = {
+ FUNIT_CFG(I2C5, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
+ FUNIT_CFG(SBC4, PLLP, 33333, spipad, ARRAY_SIZE(spipad)),
+};
+
void bootblock_mainboard_early_init(void)
{
soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
@@ -70,24 +82,15 @@ static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
-
- /* The PMIC is on I2C5 and can run at 400 KHz. */
- clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
-
- /* TODO: We should be able to set this to 50MHz, but that did not seem
- * reliable. */
- clock_configure_source(sbc4, PLLP, 33333);
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
- /* Enable PMIC I2C controller. */
- clock_enable_clear_reset(0, CLK_H_I2C5, 0, 0, 0, 0);
-
/* Set up the pads required to load romstage. */
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+ soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
i2c_init(4);
pmic_init(4);
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index 8364513..c4b0b44 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -25,10 +25,9 @@
#include <soc/nvidia/tegra132/spi.h>
#include <soc/addressmap.h>
#include <soc/padconfig.h>
+#include <soc/funitcfg.h>
-static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
-
-static const struct pad_config padcfgs[] = {
+static const struct pad_config sdmmc3_pad[] = {
/* MMC3(SDCARD) */
PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
PAD_CFG_SFIO(SDMMC3_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
@@ -43,6 +42,9 @@ static const struct pad_config padcfgs[] = {
/* Disable SD card reader power so it can be reset even on warm boot.
Payloads must enable power before accessing SD card slots. */
PAD_CFG_GPIO_OUT0(KB_ROW0, PINMUX_PULL_NONE),
+};
+
+static const struct pad_config sdmmc4_pad[] = {
/* MMC4 (eMMC) */
PAD_CFG_SFIO(SDMMC4_CLK, PINMUX_INPUT_ENABLE, SDMMC4),
PAD_CFG_SFIO(SDMMC4_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
@@ -56,13 +58,10 @@ static const struct pad_config padcfgs[] = {
PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
};
-static void configure_clocks(void)
-{
- /* MMC */
- clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0);
- clock_configure_source(sdmmc3, PLLP, 48000);
- clock_configure_source(sdmmc4, PLLP, 48000);
-}
+static const struct funit_cfg funitcfgs[] = {
+ FUNIT_CFG(SDMMC3, PLLP, 48000, sdmmc3_pad, ARRAY_SIZE(sdmmc3_pad)),
+ FUNIT_CFG(SDMMC4, PLLP, 48000, sdmmc4_pad, ARRAY_SIZE(sdmmc4_pad)),
+};
static void setup_ec_spi(void)
{
@@ -73,9 +72,7 @@ static void setup_ec_spi(void)
static void mainboard_init(device_t dev)
{
- configure_clocks();
-
- soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+ soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
setup_ec_spi();
}
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index b54058f..e82f5ad 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -23,15 +23,20 @@
#include <soc/clock.h>
#include <soc/padconfig.h>
#include <soc/nvidia/tegra/i2c.h>
-
-static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+#include <soc/funitcfg.h>
static const struct pad_config padcfgs[] = {
/* SOC_WARM_RESET_L */
PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP),
+};
+
+static const struct pad_config i2cpad[] = {
/* TPM I2C */
PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+};
+
+static const struct pad_config spipad[] = {
/* EC on SPI1: mosi, miso, clk, cs */
PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1),
PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1),
@@ -39,23 +44,16 @@ static const struct pad_config padcfgs[] = {
PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1),
};
-static void configure_clocks(void)
-{
- /* EC on SPI1 controller. */
- clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
- clock_configure_source(sbc1, CLK_M, 3000);
-
- /* TPM on I2C3 controller */
- clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
- clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
-}
+static const struct funit_cfg funitcfgs[] = {
+ FUNIT_CFG(SBC1, CLK_M, 3000, spipad, ARRAY_SIZE(spipad)),
+ FUNIT_CFG(I2C3, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
+};
void romstage_mainboard_init(void)
{
- configure_clocks();
-
/* Bring up controller interfaces for ramstage loading. */
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+ soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
/* TPM I2C bus */
i2c_init(2);
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