[coreboot-gerrit] Patch set updated for coreboot: a99aed0 tegra132: introduce romstage_mainboard_init()

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8901

-gerrit

commit a99aed02361584a9dfdd6c087e9d6c5f0f504f5d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Aug 1 16:50:27 2014 -0500

    tegra132: introduce romstage_mainboard_init()
    
    Instead of calling out with function names all the possible
    combinations of interface and device provide one call to the
    mainboard to configure all the necessary bits.
    
    BUG=chrome-os-partner:31104
    BUG=chrome-os-partner:31105
    BRANCH=None
    TEST=Built and ran on rush.
    
    Change-Id: Id7817e85065884d64f90ac514bf698bf539f2afe
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f4f63f5965d403a32872d7b52c180694f5ef679d
    Original-Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/210838
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
 src/mainboard/google/rush/romstage.c           | 10 ++++++--
 src/mainboard/google/rush_ryu/romstage.c       | 15 ++++++------
 src/soc/nvidia/tegra132/include/soc/romstage.h |  6 ++---
 src/soc/nvidia/tegra132/romstage.c             | 32 +++++++++++++++++++++-----
 4 files changed, 45 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index 5e74e71..b4d9714 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -34,7 +34,7 @@ static void configure_tpm_i2c_bus(void)
 	i2c_init(2);
 }
 
-void mainboard_init_tpm_i2c(void)
+static void mainboard_init_tpm_i2c(void)
 {
 	clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
 
@@ -51,7 +51,7 @@ void mainboard_init_tpm_i2c(void)
 	configure_tpm_i2c_bus();
 }
 
-void mainboard_init_ec_spi(void)
+static void mainboard_init_ec_spi(void)
 {
 	clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
 
@@ -75,6 +75,12 @@ void mainboard_init_ec_spi(void)
 	clock_configure_source(sbc1, CLK_M, 500);
 }
 
+void romstage_mainboard_init(void)
+{
+	mainboard_init_tpm_i2c();
+	mainboard_init_ec_spi();
+}
+
 void mainboard_configure_pmc(void)
 {
 }
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index 1c08718..4ebb8ed 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -38,7 +38,7 @@ static void configure_ec_i2c_bus(void)
 	i2c_init(1);
 }
 
-void mainboard_init_tpm_i2c(void)
+static void mainboard_init_tpm_i2c(void)
 {
 	clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
 
@@ -54,12 +54,7 @@ void mainboard_init_tpm_i2c(void)
 	configure_tpm_i2c_bus();
 }
 
-void mainboard_init_ec_spi(void)
-{
-	/* Empty - Ryu uses I2C to communicate with the EC */
-}
-
-void mainboard_init_ec_i2c(void)
+static void mainboard_init_ec_i2c(void)
 {
 	clock_enable_clear_reset(0, CLK_H_I2C2, 0, 0, 0, 0);
 
@@ -73,6 +68,12 @@ void mainboard_init_ec_i2c(void)
 	configure_ec_i2c_bus();
 }
 
+void romstage_mainboard_init(void)
+{
+	mainboard_init_tpm_i2c();
+	mainboard_init_ec_i2c();
+}
+
 void mainboard_configure_pmc(void)
 {
 }
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h
index dcf6ad6..14358d8 100644
--- a/src/soc/nvidia/tegra132/include/soc/romstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/romstage.h
@@ -20,10 +20,10 @@
 #ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
 #define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
 
+void romstage(void);
+void romstage_mainboard_init(void);
+
 void mainboard_configure_pmc(void);
 void mainboard_enable_vdd_cpu(void);
-void mainboard_init_tpm_i2c(void);
-void mainboard_init_ec_spi(void);
-void mainboard_init_ec_i2c(void);
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index be431f7..8d12ded 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -32,7 +32,25 @@
 #include <soc/clock.h>
 #include <soc/romstage.h>
 
-void romstage(void);
+void __attribute__((weak)) romstage_mainboard_init(void)
+{
+	/* Default empty implementation. */
+}
+
+static void *load_ramstage(void)
+{
+	void *entry;
+	/*
+	 * This platform does not need to cache a loaded ramstage nor do we
+	 * go down this path on resume. Therefore, no romstage_handoff is
+	 * required.
+	 */
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+				CONFIG_CBFS_PREFIX "/ramstage");
+
+	return entry;
+}
+
 void romstage(void)
 {
 	void *entry;
@@ -67,12 +85,14 @@ void romstage(void)
 	ccplex_load_mts();
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
-	mainboard_init_tpm_i2c();
-	mainboard_init_ec_spi();
-	mainboard_init_ec_i2c();
+	romstage_mainboard_init();
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-				CONFIG_CBFS_PREFIX "/ramstage");
+	entry = load_ramstage();
+
+	if (entry == NULL) {
+		printk(BIOS_INFO, "T132 romstage: error loading ramstage\n");
+		clock_halt_avp();
+	}
 
 	cbmemc_reinit();