[coreboot-gerrit] New patch to review for coreboot: b99f144 broadwell: Add config option to disable DSP power gating in D3

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8947

-gerrit

commit b99f144952ebfeb7f30dfe91df0b81adb47e99b9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Jul 31 10:41:56 2014 -0700

    broadwell: Add config option to disable DSP power gating in D3
    
    This is useful for debug and testing.
    
    BUG=chrome-os-partner:29649
    BRANCH=None
    TEST=build and boot on samus
    
    Original-Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/210599
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit 2831154af4f33717489cb0b62aef228fb8f7c2e2)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ie622df02d9ab219cefce5f11332e010b47e3ec6e
---
 src/soc/intel/broadwell/adsp.c | 20 +++++++++++++++-----
 src/soc/intel/broadwell/chip.h |  3 +++
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 4137215..9ecbe95 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -69,12 +69,22 @@ static void adsp_init(struct device *dev)
 
 	/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
 	tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
-	if (pch_is_wpt()) {
-		tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
-		tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+	if (config->adsp_d3_pg_disable) {
+		if (pch_is_wpt()) {
+			tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
+			tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+		} else {
+			tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
+			tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+		}
 	} else {
-		tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
-		tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+		if (pch_is_wpt()) {
+			tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
+			tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+		} else {
+			tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
+			tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+		}
 	}
 	pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
 
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index a3b716b..e433483 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -84,6 +84,9 @@ struct soc_intel_broadwell_config {
 	uint8_t sio_i2c0_voltage;
 	uint8_t sio_i2c1_voltage;
 
+	/* Disable ADSP power gating in D3 */
+	uint8_t adsp_d3_pg_disable;
+
 	/*
 	 * Clock Disable Map:
 	 * [21:16] = CLKOUT_PCIE# 5-0