[coreboot-gerrit] Patch set updated for coreboot: 1cd0101 rush: Add usb support for rush in coreboot

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8937

-gerrit

commit 1cd010189e0a5e2997b848dbc3819771bdb9be29
Author: Furquan Shaikh <furquan at google.com>
Date:   Tue Aug 5 21:14:54 2014 -0700

    rush: Add usb support for rush in coreboot
    
    BUG=chrome-os-partner:31293
    BRANCH=None
    TEST=With non-cacheable memory region and dma range addition, booting from usb
    reaches the same point as mmc.
    
    Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd
    Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/211039
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
 src/mainboard/google/rush/mainboard.c | 18 ++++++++++++++++++
 src/soc/nvidia/tegra132/Makefile.inc  |  1 +
 2 files changed, 19 insertions(+)

diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index 35417f0..a143972 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -28,6 +28,7 @@
 #include <soc/addressmap.h>
 #include <soc/padconfig.h>
 #include <soc/funitcfg.h>
+#include <soc/nvidia/tegra/usb.h>
 
 static const struct pad_config sdmmc3_pad[] = {
 	/* MMC3(SDCARD) */
@@ -60,6 +61,13 @@ static const struct pad_config sdmmc4_pad[] = {
 	PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
 };
 
+static const struct pad_config padcfgs[] = {
+	/* We pull the USB VBUS signals up but keep them as inputs since the
+	 * voltage source likes to drive them low on overcurrent conditions */
+	PAD_CFG_GPIO_INPUT(USB_VBUS_EN0, PINMUX_PULL_UP),
+	PAD_CFG_GPIO_INPUT(USB_VBUS_EN1, PINMUX_PULL_UP),
+};
+
 static const struct funit_cfg funitcfgs[] = {
 	FUNIT_CFG(SDMMC3, PLLP, 48000, sdmmc3_pad, ARRAY_SIZE(sdmmc3_pad)),
 	FUNIT_CFG(SDMMC4, PLLP, 48000, sdmmc4_pad, ARRAY_SIZE(sdmmc4_pad)),
@@ -72,11 +80,21 @@ static void setup_ec_spi(void)
 	spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
 }
 
+static void setup_usb(void)
+{
+	clock_enable_clear_reset(CLK_L_USBD, CLK_H_USB3, 0, 0, 0, 0);
+
+	usb_setup_utmip((void *)TEGRA_USBD_BASE);
+	usb_setup_utmip((void *)TEGRA_USB3_BASE);
+}
+
 static void mainboard_init(device_t dev)
 {
+	soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
 	soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
 
 	setup_ec_spi();
+	setup_usb();
 }
 
 static void mainboard_enable(device_t dev)
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 6bff52f..0411f74 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -62,6 +62,7 @@ ramstage-y += ../tegra/pinmux.c
 ramstage-y += ramstage.c
 ramstage-y += mmu_operations.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-y += ../tegra/usb.c
 
 modules_arm-y += monotonic_timer.c
 VBOOT_STUB_DEPS += $(obj)/soc/nvidia/tegra132/monotonic_timer.rmodules_arm.o