[coreboot-gerrit] Patch merged into coreboot/master: c33ce35 rk3288: add ddr driver

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c33ce3554ddc73635084e6e71b5e4f7dae021926
Author: Jinkun Hong <jinkun.hong at rock-chips.com>
Date:   Thu Aug 28 09:37:22 2014 -0700

    rk3288: add ddr driver
    
    Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
    ddr timing config file in src\mainboard\google\veyron\sdram_inf
    Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).
    
    BUG=chrome-os-partner:29778
    TEST=Build coreboot
    
    Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321
    Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
    Original-Signed-off-by: jinkun.hong <jinkun.hong at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/209465
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Commit-Queue: Julius Werner <jwerner at chromium.org>
    Reviewed-on: http://review.coreboot.org/8865
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/8865 for details.

-gerrit