[coreboot-gerrit] Patch set updated for coreboot: 208de68 ryu: convert hardware initialization to funit API
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Mar 24 13:37:52 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8930
-gerrit
commit 208de6815efc80f9530021279969f23845fa6b4c
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Aug 13 13:27:14 2014 -0500
ryu: convert hardware initialization to funit API
Use the new funit API to do all the dirty work.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through depthcharge and into recovery just like
before.
Change-Id: I8625a06dd847bd3dcfc3ce5a50a31d6aff0b860f
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: ebc04a174269ae072eda804e172fd24362f417d2
Original-Change-Id: Ief2d81c5569c33a90fc9458d741edef1dcbd8239
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212152
Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
src/mainboard/google/rush_ryu/bootblock.c | 48 ++++++++++++++++---------------
src/mainboard/google/rush_ryu/mainboard.c | 16 ++++-------
src/mainboard/google/rush_ryu/romstage.c | 34 +++++++++++-----------
3 files changed, 47 insertions(+), 51 deletions(-)
diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c
index e5975d2..ffcffd3 100644
--- a/src/mainboard/google/rush_ryu/bootblock.c
+++ b/src/mainboard/google/rush_ryu/bootblock.c
@@ -23,6 +23,7 @@
#include <soc/addressmap.h>
#include <soc/bootblock.h>
#include <soc/clock.h>
+#include <soc/funitcfg.h>
#include <soc/padconfig.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra132/clk_rst.h>
@@ -30,8 +31,6 @@
#include "pmic.h"
-static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
-
static const struct pad_config uart_console_pads[] = {
/* UARTA: tx and rx. */
PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3),
@@ -45,6 +44,26 @@ static const struct pad_config uart_console_pads[] = {
PAD_CFG_UNUSED(UART2_CTS_N),
};
+static const struct pad_config pmic_pads[] = {
+ PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
+ PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
+};
+
+static const struct pad_config spiflash_pads[] = {
+ /* mosi, miso, clk, cs0 */
+ PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
+ PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
+ PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4),
+ PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4),
+};
+
+static const struct funit_cfg funits[] = {
+ /* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */
+ FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)),
+ /* SPI flash at 33MHz on SPI4 controller. */
+ FUNIT_CFG(SBC4, PLLP, 33333, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
+};
+
void bootblock_mainboard_early_init(void)
{
soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
@@ -52,41 +71,24 @@ void bootblock_mainboard_early_init(void)
static void set_clock_sources(void)
{
+ struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
-
- clock_configure_source(mselect, PLLP, 102000);
-
- /* The PMIC is on I2C5 and can run at 400 KHz. */
- clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
-
- /* TODO: We should be able to set this to 50MHz, but that did not seem
- * reliable. */
- clock_configure_source(sbc4, PLLP, 33333);
}
static const struct pad_config padcfgs[] = {
/* Board build id bits 1:0 */
PAD_CFG_GPIO_INPUT(KB_COL4, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
- /* PMIC i2C bus */
- PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
- PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
- /* SPI fLash: mosi, miso, clk, cs0 */
- PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
- PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
- PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4),
- PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4),
};
void bootblock_mainboard_init(void)
{
set_clock_sources();
- /* Enable PMIC I2C controller. */
- clock_enable_clear_reset(0, CLK_H_I2C5, 0, 0, 0, 0);
-
- /* Set up the pads required to load romstage. */
+ /* Set up controllers and pads to load romstage. */
+ soc_configure_funits(funits, ARRAY_SIZE(funits));
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
i2c_init(4);
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 1e80b5b..426c30c 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -24,11 +24,10 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
+#include <soc/funitcfg.h>
#include <soc/padconfig.h>
#include <soc/nvidia/tegra132/clk_rst.h>
-static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
-
static const struct pad_config mmcpads[] = {
/* MMC4 (eMMC) */
PAD_CFG_SFIO(SDMMC4_CLK, PINMUX_INPUT_ENABLE|PINMUX_PULL_DOWN, SDMMC4),
@@ -43,17 +42,14 @@ static const struct pad_config mmcpads[] = {
PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
};
-static void init_mmc(void)
-{
- clock_enable_clear_reset(CLK_L_SDMMC4, 0, 0, 0, 0, 0);
- clock_configure_source(sdmmc4, PLLP, 48000);
-
- soc_configure_pads(mmcpads, ARRAY_SIZE(mmcpads));
-}
+static const struct funit_cfg funits[] = {
+ /* MMC on SDMMC4 controller at 48MHz. */
+ FUNIT_CFG(SDMMC4, PLLP, 48000, mmcpads, ARRAY_SIZE(mmcpads)),
+};
static void mainboard_init(device_t dev)
{
- init_mmc();
+ soc_configure_funits(funits, ARRAY_SIZE(funits));
}
static void mainboard_enable(device_t dev)
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index 307c1f7..f6de3d5 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -19,41 +19,39 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
+#include <soc/funitcfg.h>
#include <soc/padconfig.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/romstage.h>
-static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
-
static const struct pad_config padcfgs[] = {
/* AP_SYS_RESET_L */
PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP),
- /* TPM on I2C3 */
+ /* WP_L */
+ PAD_CFG_GPIO_INPUT(KB_ROW1, PINMUX_PULL_NONE),
+};
+
+static const struct pad_config tpm_pads[] = {
PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
- /* EC on I2C2 - pulled to 3.3V */
+};
+
+static const struct pad_config ec_i2c_pads[] = {
PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2),
PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2),
- /* WP_L */
- PAD_CFG_GPIO_INPUT(KB_ROW1, PINMUX_PULL_NONE),
};
-static void configure_clocks(void)
-{
- /* TPM on I2C3 */
- clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
- clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
-
- /* EC on I2C2 */
- clock_enable_clear_reset(0, CLK_H_I2C2, 0, 0, 0, 0);
- clock_configure_i2c_scl_freq(i2c2, PLLP, 100);
-}
+static const struct funit_cfg funits[] = {
+ /* TPM on I2C3 @ 400kHz */
+ FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
+ /* EC on I2C2 - pulled to 3.3V @ 100kHz */
+ FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)),
+};
void romstage_mainboard_init(void)
{
- configure_clocks();
-
/* Bring up controller interfaces for ramstage loading. */
+ soc_configure_funits(funits, ARRAY_SIZE(funits));
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
/* TPM */
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