[coreboot-gerrit] New patch to review for coreboot: daddc75 tegra132: output chip information and MTS version

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8905

-gerrit

commit daddc75f030c63b0619f03d0bfca2f9600777678
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Aug 4 11:40:45 2014 -0500

    tegra132: output chip information and MTS version
    
    It's helpful to be able to track this information. Therefore
    dump it in to the console log.
    
    BRANCH=None
    BUG=chrome-os-partner:31126
    TEST=Built and ran on rush. Revision information is put out on the
         console.
    
    Change-Id: I22e7d222259c1179b90edda6d7807559357f6725
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02
    Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/210903
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
 src/soc/nvidia/tegra/apbmisc.c       | 13 +++++++++++++
 src/soc/nvidia/tegra/apbmisc.h       | 11 +++++++++++
 src/soc/nvidia/tegra132/Makefile.inc |  1 +
 src/soc/nvidia/tegra132/soc.c        | 14 ++++++++++++++
 4 files changed, 39 insertions(+)

diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c
index 5983d54..3fc0ef7 100644
--- a/src/soc/nvidia/tegra/apbmisc.c
+++ b/src/soc/nvidia/tegra/apbmisc.c
@@ -33,3 +33,16 @@ void clamp_tristate_inputs(void)
 {
 	write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
 }
+
+void tegra_revision_info(struct tegra_revision *id)
+{
+	uintptr_t gp_hidrev= (uintptr_t)TEGRA_APB_MISC_BASE + MISC_GP_HIDREV;
+	uint32_t reg;
+
+	reg = read32((void *)(gp_hidrev));
+
+	id->hid_fam = (reg >> 0) & 0x0f;
+	id->chip_id = (reg >> 8) & 0xff;
+	id->major = (reg >> 4) & 0x0f;
+	id->minor = (reg >> 16) & 0x07;
+}
diff --git a/src/soc/nvidia/tegra/apbmisc.h b/src/soc/nvidia/tegra/apbmisc.h
index 2f1811a..38cd527 100644
--- a/src/soc/nvidia/tegra/apbmisc.h
+++ b/src/soc/nvidia/tegra/apbmisc.h
@@ -34,8 +34,19 @@ struct apbmisc {
 
 #define PP_PINMUX_CLAMP_INPUTS		(1 << 0)
 
+enum {
+	MISC_GP_HIDREV = 0x804
+};
+
+struct tegra_revision {
+	int hid_fam;
+	int chip_id;
+	int major;
+	int minor;
+};
 
 void enable_jtag(void);
 void clamp_tristate_inputs(void);
+void tegra_revision_info(struct tegra_revision *id);
 
 #endif	/* __SOC_NVIDIA_TEGRA_APBMISC_H__ */
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 756560d..868da42 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -49,6 +49,7 @@ ramstage-y += i2c.c
 ramstage-y += dma.c
 ramstage-y += monotonic_timer.c
 ramstage-y += padconfig.c
+ramstage-y += ../tegra/apbmisc.c
 ramstage-y += ../tegra/gpio.c
 ramstage-y += ../tegra/i2c.c
 ramstage-y += ../tegra/pinmux.c
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index f4ef928..84b0507 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -23,6 +23,7 @@
 #include <arch/io.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/addressmap.h>
+#include <soc/nvidia/tegra/apbmisc.h>
 
 static void soc_read_resources(device_t dev)
 {
@@ -79,7 +80,20 @@ static void enable_tegra132_dev(device_t dev)
 	dev->ops = &soc_ops;
 }
 
+static void tegra132_init(void *chip_info)
+{
+	struct tegra_revision rev;
+
+	tegra_revision_info(&rev);
+
+	printk(BIOS_INFO, "chip %x rev %02x.%x\n",
+		rev.chip_id, rev.major, rev.minor);
+
+	printk(BIOS_INFO, "MTS build %08x\n", raw_read_aidr_el1());
+}
+
 struct chip_operations soc_nvidia_tegra132_ops = {
 	CHIP_NAME("SOC Nvidia Tegra132")
+	.init = tegra132_init,
 	.enable_dev = enable_tegra132_dev,
 };