[coreboot-gerrit] New patch to review for coreboot: 1098569 rush: Add support for chromeos_ec

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8898

-gerrit

commit 10985690b442d4707498b05e8c64c7b6cec40009
Author: Furquan Shaikh <furquan at google.com>
Date:   Tue Jul 29 18:47:16 2014 -0700

    rush: Add support for chromeos_ec
    
    BUG=chrome-os-partner:31032
    BRANCH=None
    TEST=Compiles successfully and ec error fixed while booting.
    
    Change-Id: I7bb78b8986931407ee67f33e83b9d887bea7ac70
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5447adb964276b9e13399ac93140ae763a149aad
    Original-Change-Id: I02172a30863b7b97892289e880c29f2d71220fda
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/210436
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
 src/mainboard/google/rush/Kconfig              |  8 ++++++++
 src/mainboard/google/rush/mainboard.c          |  9 +++++++++
 src/mainboard/google/rush/romstage.c           | 24 ++++++++++++++++++++++++
 src/soc/nvidia/tegra132/include/soc/romstage.h |  1 +
 src/soc/nvidia/tegra132/romstage.c             |  1 +
 5 files changed, 43 insertions(+)

diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index 87e742e..eaae86c 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -23,6 +23,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select BOARD_ID_SUPPORT
 	select CHROMEOS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_SPI
+	select EC_SOFTWARE_SYNC
+	select SPI_FLASH
 	select SOC_NVIDIA_TEGRA132
 	select MAINBOARD_HAS_BOOTBLOCK_INIT
 	select VIRTUAL_DEV_SWITCH
@@ -87,4 +91,8 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x20
 
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	hex
+	default 1
+
 endif # BOARD_GOOGLE_RUSH
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index 6db314f..fd8a469 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -23,6 +23,7 @@
 #include <soc/clock.h>
 #include <soc/nvidia/tegra132/gpio.h>
 #include <soc/nvidia/tegra132/clk_rst.h>
+#include <soc/nvidia/tegra132/spi.h>
 #include <soc/addressmap.h>
 
 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@@ -84,11 +85,19 @@ static void init_mmc(void)
 
 }
 
+static void setup_ec_spi(void)
+{
+	struct tegra_spi_channel *spi;
+
+	spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
+}
+
 static void mainboard_init(device_t dev)
 {
 	clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0);
 
 	init_mmc();
+	setup_ec_spi();
 }
 
 static void mainboard_enable(device_t dev)
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index 7c01a30..5e74e71 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -51,6 +51,30 @@ void mainboard_init_tpm_i2c(void)
 	configure_tpm_i2c_bus();
 }
 
+void mainboard_init_ec_spi(void)
+{
+	clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
+
+	// SPI1 MOSI
+	pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
+						 PINMUX_PULL_NONE |
+						 PINMUX_INPUT_ENABLE);
+	// SPI1 MISO
+	pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
+						 PINMUX_PULL_NONE |
+						 PINMUX_INPUT_ENABLE);
+	// SPI1 SCLK
+	pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
+						 PINMUX_PULL_NONE |
+						 PINMUX_INPUT_ENABLE);
+	// SPI1 CS0
+	pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
+						 PINMUX_PULL_NONE |
+						 PINMUX_INPUT_ENABLE);
+
+	clock_configure_source(sbc1, CLK_M, 500);
+}
+
 void mainboard_configure_pmc(void)
 {
 }
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h
index f669121..d5fabd2 100644
--- a/src/soc/nvidia/tegra132/include/soc/romstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/romstage.h
@@ -23,5 +23,6 @@
 void mainboard_configure_pmc(void);
 void mainboard_enable_vdd_cpu(void);
 void mainboard_init_tpm_i2c(void);
+void mainboard_init_ec_spi(void);
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 69271f0..b9932f2 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -68,6 +68,7 @@ void romstage(void)
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
 	mainboard_init_tpm_i2c();
+	mainboard_init_ec_spi();
 
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
 				CONFIG_CBFS_PREFIX "/ramstage");