[coreboot-gerrit] Patch set updated for coreboot: b6445eb veyron: Rename "veyron" board to "veyron_pinky"
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Mar 23 19:50:55 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8869
-gerrit
commit b6445ebc8641b8b4861f45cf8e99748a9e8abc22
Author: Julius Werner <jwerner at chromium.org>
Date: Wed Sep 10 15:10:45 2014 -0700
veyron: Rename "veyron" board to "veyron_pinky"
We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".
CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.
Change-Id: I88bf5cc2da7c2f969ea184b5f12affaa94045a06
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: aa8ec24b63d11798fec1993091b113a0c0938c7a
Original-Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217674
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
src/mainboard/google/Kconfig | 6 +-
src/mainboard/google/veyron/Kconfig | 63 ---------
src/mainboard/google/veyron/Makefile.inc | 27 ----
src/mainboard/google/veyron/chromeos.c | 112 ----------------
src/mainboard/google/veyron/devicetree.cb | 49 -------
src/mainboard/google/veyron/mainboard.c | 143 ---------------------
src/mainboard/google/veyron/pmic.c | 85 ------------
src/mainboard/google/veyron/pmic.h | 23 ----
src/mainboard/google/veyron/romstage.c | 83 ------------
src/mainboard/google/veyron/sdram_configs.c | 75 -----------
.../veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc | 77 -----------
.../veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 -----------
.../google/veyron/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_pinky/Kconfig | 63 +++++++++
src/mainboard/google/veyron_pinky/Makefile.inc | 27 ++++
src/mainboard/google/veyron_pinky/chromeos.c | 112 ++++++++++++++++
src/mainboard/google/veyron_pinky/devicetree.cb | 49 +++++++
src/mainboard/google/veyron_pinky/mainboard.c | 143 +++++++++++++++++++++
src/mainboard/google/veyron_pinky/pmic.c | 85 ++++++++++++
src/mainboard/google/veyron_pinky/pmic.h | 23 ++++
src/mainboard/google/veyron_pinky/romstage.c | 83 ++++++++++++
src/mainboard/google/veyron_pinky/sdram_configs.c | 75 +++++++++++
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 77 +++++++++++
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 +++++++++++
.../google/veyron_pinky/sdram_inf/sdram-unused.inc | 3 +
25 files changed, 821 insertions(+), 821 deletions(-)
diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig
index fb1ead6..7b227a4 100644
--- a/src/mainboard/google/Kconfig
+++ b/src/mainboard/google/Kconfig
@@ -59,8 +59,8 @@ config BOARD_GOOGLE_STORM
bool "Storm"
config BOARD_GOOGLE_STOUT
bool "Stout"
-config BOARD_GOOGLE_VEYRON
- bool "Veyron"
+config BOARD_GOOGLE_VEYRON_PINKY
+ bool "Veyron_Pinky"
endchoice
@@ -83,7 +83,7 @@ source "src/mainboard/google/samus/Kconfig"
source "src/mainboard/google/slippy/Kconfig"
source "src/mainboard/google/storm/Kconfig"
source "src/mainboard/google/stout/Kconfig"
-source "src/mainboard/google/veyron/Kconfig"
+source "src/mainboard/google/veyron_pinky/Kconfig"
config MAINBOARD_VENDOR
string "Mainboard Vendor"
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
deleted file mode 100644
index f54917c..0000000
--- a/src/mainboard/google/veyron/Kconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-if BOARD_GOOGLE_VEYRON
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CHROMEOS
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select BOARD_ROMSIZE_KB_4096
-
-config MAINBOARD_DIR
- string
- default google/veyron
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRAM_DMA_START
- hex
- default 0x10000000
-
-config DRAM_DMA_SIZE
- hex
- default 0x00200000
-
-config DRAM_SIZE_MB
- int
- default 2048
-
-endif # BOARD_GOOGLE_VEYRON
diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc
deleted file mode 100644
index 0b0e328..0000000
--- a/src/mainboard/google/veyron/Makefile.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-romstage-y += romstage.c
-romstage-y += chromeos.c
-romstage-y += sdram_configs.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += chromeos.c
-ramstage-y += pmic.c
-
diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c
deleted file mode 100644
index 4e1e50c..0000000
--- a/src/mainboard/google/veyron/chromeos.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/rockchip/rk3288/gpio.h>
-
-#define GPIO_WP (gpio_t){.port = 7, .bank = GPIO_A, .idx = 6}
-#define GPIO_LID (gpio_t){.port = 7, .bank = GPIO_B, .idx = 5}
-#define GPIO_POWER (gpio_t){.port = 0, .bank = GPIO_A, .idx = 5}
-#define GPIO_RECOVERY (gpio_t){.port = 0, .bank = GPIO_B, .idx = 1}
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input_pullup(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get_in_value(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = gpio_get_in_value(GPIO_LID);
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = gpio_get_in_value(GPIO_POWER);
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get_in_value(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get_in_value(GPIO_WP);
-}
-
diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb
deleted file mode 100644
index 0acbae9..0000000
--- a/src/mainboard/google/veyron/devicetree.cb
+++ /dev/null
@@ -1,49 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- #SCREEN_RGB
- register "screen_type" = "2"
- #LVDS_8BIT_2
- register "lvds_format" = "1"
- #OUT_D888_P666
- register "out_face" = "33"
- register "clock_frequency" = "71000000"
- register "hactive" = "1280"
- register "vactive" = "800"
- register "hback_porch" = "100"
- register "hfront_porch" = "18"
- register "vback_porch" = "8"
- register "vfront_porch" = "6"
- register "hsync_len" = "10"
- register "vsync_len" = "2"
- register "hsync_active" = "0"
- register "vsync_active" = "0"
- register "de_active" = "0"
- register "pixelclk_active" = "0"
- register "swap_rb" = "0"
- register "swap_rg" = "0"
- register "swap_gb" = "0"
- #LCD_EN_GPIO:GPIO7_A3
- register "lcd_en_gpio" = "0xff7e0004"
- #LCD_CS_GPIO:GPIO7_A4
- register "lcd_cs_gpio" = "0xff7e0005"
-end
diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c
deleted file mode 100644
index 349240f..0000000
--- a/src/mainboard/google/veyron/mainboard.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/cache.h>
-#include <delay.h>
-#include <edid.h>
-#include <vbe.h>
-#include <boot/coreboot_tables.h>
-#include <device/i2c.h>
-#include <soc/rockchip/rk3288/gpio.h>
-#include <soc/rockchip/rk3288/soc.h>
-#include <soc/rockchip/rk3288/pmu.h>
-#include <soc/rockchip/rk3288/clock.h>
-#include <soc/rockchip/rk3288/spi.h>
-#include "pmic.h"
-
-#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
-#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
-#define DRAM_END (DRAM_START + DRAM_SIZE)
-
-static void setup_gpio(void)
-{
- /*SOC and TPM reset GPIO, active high.*/
- gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 2}, 0);
-
- /* Configure GPIO for lcd_bl_en */
- gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 2}, 1);
-
- /*Configure backlight PWM 100% brightness*/
- gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 0}, 0);
-
- /* Configure GPIO for lcd_en */
- gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 7}, 1);
-}
-
-static void setup_iomux(void)
-{
- /*i2c0 for pmic*/
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
-
- /*i2c1 for tpm*/
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
-
- /*i2c2 for codec*/
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);
-
- writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
- writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
- writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
- writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
- writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
- writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
- writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
- writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
-}
-
-static void setup_usb_poweron(void)
-{
- /* Configure GPIO for usb1_pwr_en */
- gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 3}, 1);
-
- /* Configure GPIO for usb2_pwr_en */
- gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 4}, 1);
-
- /* Configure GPIO for 5v_drv */
- gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 3}, 1);
-}
-
-static void configure_sdmmc(void)
-{
- /* Configure GPIO for sd_en */
- gpio_output((gpio_t){.port = 7, .bank = GPIO_C, .idx = 5}, 1);
-
- /* Configure GPIO for sd_detec */
- gpio_input_pullup((gpio_t){.port = 7, .bank = GPIO_A, .idx = 5});
-
- /*use sdmmc0 io, disable JTAG function*/
- writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
-}
-
-static void configure_emmc(void)
-{
- /* Configure GPIO for emmc_pwrctrl */
- gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 4}, 1);
-}
-
-static void configure_i2s(void)
-{
- /*AUDIO IO domain 1.8V voltage selection*/
- writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
- rkclk_configure_i2s(12288000);
-}
-
-static void mainboard_init(device_t dev)
-{
- setup_iomux();
- pmic_init(0);
- setup_gpio();
- setup_usb_poweron();
- configure_sdmmc();
- configure_emmc();
- configure_i2s();
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = CONFIG_DRAM_DMA_START;
- dma->range_size = CONFIG_DRAM_DMA_SIZE;
-}
diff --git a/src/mainboard/google/veyron/pmic.c b/src/mainboard/google/veyron/pmic.c
deleted file mode 100644
index 2e6f0ab..0000000
--- a/src/mainboard/google/veyron/pmic.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/i2c.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "pmic.h"
-
-#define RK808_ADDR 0x1b
-#define LOD1EN (1 << 0)
-#define LOD2EN (1 << 1)
-#define LOD3EN (1 << 2)
-#define LOD4EN (1 << 3)
-#define LOD5EN (1 << 4)
-#define LOD6EN (1 << 5)
-#define LOD7EN (1 << 6)
-#define LOD8EN (1 << 7)
-
-#define LDO_BASE18V 18
-#define LDO_BASE08V 8
-#define LDOVSEL(mV, base) (mV/100 - base)
-
-struct rk808_reg {
- u8 reg;
- u8 val;
-};
-
-enum {
- LDO_EN = 0x24,
- LDO1_ONSEL = 0x3B,
- LDO1_SLPSEL,
- LDO2_ONSEL,
- LDO2_SLPSEL,
- LDO3_ONSEL,
- LDO3_SLPSEL,
- LDO4_ONSEL,
- LDO4_SLPSEL,
- LDO5_ONSEL,
- LDO5_SLPSEL,
- LDO6_ONSEL,
- LDO6_SLPSEL,
- LDO7_ONSEL,
- LDO7_SLPSEL,
- LDO8_ONSEL,
- LDO8_SLPSEL,
-};
-
-static struct rk808_reg ldo_initlist[] = {
- {LDO4_ONSEL, LDOVSEL(1800, LDO_BASE18V)}, /*vcc18_lcd*/
- {LDO5_ONSEL, LDOVSEL(1800, LDO_BASE18V)}, /*vcc18_codec*/
- {LDO6_ONSEL, LDOVSEL(1000, LDO_BASE08V)}, /*vcc10_lcd*/
- {LDO8_ONSEL, LDOVSEL(3300, LDO_BASE18V)}, /*vccio_sd*/
-};
-
-void pmic_init(unsigned int bus)
-{
- uint8_t read_reg;
- int i;
- for (i = 0; i < ARRAY_SIZE(ldo_initlist); i++) {
- struct rk808_reg *reg = &ldo_initlist[i];
- i2c_writeb(bus, RK808_ADDR, reg->reg, reg->val);
- }
-
- /*enable ldo4,ldo5,ldo6,ldo8*/
- i2c_readb(bus, RK808_ADDR, LDO_EN, &read_reg);
- i2c_writeb(bus, RK808_ADDR, LDO_EN, read_reg | LOD8EN | LOD6EN
- | LOD5EN | LOD4EN);
-}
diff --git a/src/mainboard/google/veyron/pmic.h b/src/mainboard/google/veyron/pmic.h
deleted file mode 100644
index dd6ed0b..0000000
--- a/src/mainboard/google/veyron/pmic.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__
-#define __SOC_ROCKCHIP_RK3288_PMIC_H__
-void pmic_init(unsigned int bus);
-#endif
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
deleted file mode 100644
index e1062ca..0000000
--- a/src/mainboard/google/veyron/romstage.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <armv7.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <cbmem.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <timestamp.h>
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/rockchip/rk3288/sdram.h>
-#include <soc/rockchip/rk3288/clock.h>
-#include "timer.h"
-
-void main(void)
-{
-#if CONFIG_COLLECT_TIMESTAMPS
- uint64_t start_romstage_time;
- uint64_t before_dram_time;
- uint64_t after_dram_time;
- uint64_t base_time = timestamp_get();
- start_romstage_time = timestamp_get();
-#endif
- /* used for MMU and CBMEM setup, in MB */
- u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
- u32 dram_size = CONFIG_DRAM_SIZE_MB;
- u32 dram_end = dram_start + dram_size;
-
- console_init();
-
-#if CONFIG_COLLECT_TIMESTAMPS
- before_dram_time = timestamp_get();
-#endif
- sdram_init(get_sdram_config());
-#if CONFIG_COLLECT_TIMESTAMPS
- after_dram_time = timestamp_get();
-#endif
- mmu_init();
- /* Device memory below DRAM is uncached. */
- mmu_config_range(0, dram_start, DCACHE_OFF);
- /* DRAM is cached. */
- mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
- /* A window for DMA is uncached. */
- mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
- CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
- /* The space above DRAM is uncached. */
- if (dram_end < 4096)
- mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
- dcache_mmu_enable();
-
- setup_chromeos_gpios();
-
- cbmem_initialize_empty();
-
-#if CONFIG_COLLECT_TIMESTAMPS
- timestamp_init(base_time);
- timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
- timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
- timestamp_add(TS_AFTER_INITRAM, after_dram_time);
- timestamp_add_now(TS_END_ROMSTAGE);
-#endif
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c
deleted file mode 100644
index b3600fb..0000000
--- a/src/mainboard/google/veyron/sdram_configs.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#include <arch/io.h>
-#include <string.h>
-#include <types.h>
-#include <console/console.h>
-#include <soc/rockchip/rk3288/sdram.h>
-#include <soc/rockchip/rk3288/gpio.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
-};
-
-#define GPIO_RAMCODE0 (gpio_t){.port = 8, .bank = GPIO_A, .idx = 0}
-#define GPIO_RAMCODE1 (gpio_t){.port = 8, .bank = GPIO_A, .idx = 1}
-#define GPIO_RAMCODE2 (gpio_t){.port = 8, .bank = GPIO_A, .idx = 2}
-#define GPIO_RAMCODE3 (gpio_t){.port = 8, .bank = GPIO_A, .idx = 3}
-
-u32 sdram_get_ram_code(void)
-{
- u32 code = 0;
-
- gpio_input(GPIO_RAMCODE0);
- gpio_input(GPIO_RAMCODE1);
- gpio_input(GPIO_RAMCODE2);
- gpio_input(GPIO_RAMCODE3);
-
- code = gpio_get_in_value(GPIO_RAMCODE3) << 3
- | gpio_get_in_value(GPIO_RAMCODE2) << 2
- | gpio_get_in_value(GPIO_RAMCODE1) << 1
- | gpio_get_in_value(GPIO_RAMCODE0) << 0;
-
- return code;
-}
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = sdram_get_ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 409a7ca..0000000
--- a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x35,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xBB,
- .trp = 0x8,
- .trtw = 0x4,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x6,
- .tras = 0x14,
- .trc = 0x1D,
- .trcd = 0x8,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x200,
- .txp = 0x4,
- .txpdll = 0xD,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x6,
- .tcksrx = 0x6,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x36,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x3AD48890,
- .dtpr1 = 0xBB08D8,
- .dtpr2 = 0x1002B600,
- .mr[0] = 0x840,
- .mr[1] = 0x40,
- .mr[2] = 0x8,
- .mr[3] = 0x0
- },
- .noc_timing = 0x2891E41D,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533000000,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 315e542..0000000
--- a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533000000,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig
new file mode 100644
index 0000000..ae616c7
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/Kconfig
@@ -0,0 +1,63 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_GOOGLE_VEYRON_PINKY
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CHROMEOS
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_SPI
+ select SOC_ROCKCHIP_RK3288
+ select MAINBOARD_DO_NATIVE_VGA_INIT
+ select BOARD_ROMSIZE_KB_4096
+
+config MAINBOARD_DIR
+ string
+ default google/veyron_pinky
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Veyron_Pinky"
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ hex
+ default 0
+
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 2
+
+config DRAM_DMA_START
+ hex
+ default 0x10000000
+
+config DRAM_DMA_SIZE
+ hex
+ default 0x00200000
+
+config DRAM_SIZE_MB
+ int
+ default 2048
+
+endif # BOARD_GOOGLE_VEYRON_PINKY
diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc
new file mode 100644
index 0000000..0b0e328
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/Makefile.inc
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-y += romstage.c
+romstage-y += chromeos.c
+romstage-y += sdram_configs.c
+ramstage-y += chromeos.c
+ramstage-y += mainboard.c
+ramstage-y += chromeos.c
+ramstage-y += pmic.c
+
diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c
new file mode 100644
index 0000000..4e1e50c
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/chromeos.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/rockchip/rk3288/gpio.h>
+
+#define GPIO_WP (gpio_t){.port = 7, .bank = GPIO_A, .idx = 6}
+#define GPIO_LID (gpio_t){.port = 7, .bank = GPIO_B, .idx = 5}
+#define GPIO_POWER (gpio_t){.port = 0, .bank = GPIO_A, .idx = 5}
+#define GPIO_RECOVERY (gpio_t){.port = 0, .bank = GPIO_B, .idx = 1}
+
+void setup_chromeos_gpios(void)
+{
+ gpio_input(GPIO_WP);
+ gpio_input_pullup(GPIO_LID);
+ gpio_input_pullup(GPIO_POWER);
+ gpio_input_pullup(GPIO_RECOVERY);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ int count = 0;
+
+ /* Write Protect: active low */
+ gpios->gpios[count].port = GPIO_WP.raw;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO_WP);
+ strncpy((char *)gpios->gpios[count].name, "write protect",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Recovery: active low */
+ gpios->gpios[count].port = GPIO_RECOVERY.raw;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "recovery",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Lid: active high */
+ gpios->gpios[count].port = GPIO_LID.raw;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO_LID);
+ strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Power:GPIO active high */
+ gpios->gpios[count].port = GPIO_POWER.raw;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO_POWER);
+ strncpy((char *)gpios->gpios[count].name, "power",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Developer: GPIO active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "developer",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+ gpios->count = count;
+
+ printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ uint32_t ec_events;
+
+ /* The GPIO is active low. */
+ if (!gpio_get_in_value(GPIO_RECOVERY))
+ return 1;
+
+ ec_events = google_chromeec_get_events_b();
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+ return !gpio_get_in_value(GPIO_WP);
+}
+
diff --git a/src/mainboard/google/veyron_pinky/devicetree.cb b/src/mainboard/google/veyron_pinky/devicetree.cb
new file mode 100644
index 0000000..0acbae9
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/devicetree.cb
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# TODO fill with Versatile Express board data in QEMU.
+chip soc/rockchip/rk3288
+ device cpu_cluster 0 on end
+ #SCREEN_RGB
+ register "screen_type" = "2"
+ #LVDS_8BIT_2
+ register "lvds_format" = "1"
+ #OUT_D888_P666
+ register "out_face" = "33"
+ register "clock_frequency" = "71000000"
+ register "hactive" = "1280"
+ register "vactive" = "800"
+ register "hback_porch" = "100"
+ register "hfront_porch" = "18"
+ register "vback_porch" = "8"
+ register "vfront_porch" = "6"
+ register "hsync_len" = "10"
+ register "vsync_len" = "2"
+ register "hsync_active" = "0"
+ register "vsync_active" = "0"
+ register "de_active" = "0"
+ register "pixelclk_active" = "0"
+ register "swap_rb" = "0"
+ register "swap_rg" = "0"
+ register "swap_gb" = "0"
+ #LCD_EN_GPIO:GPIO7_A3
+ register "lcd_en_gpio" = "0xff7e0004"
+ #LCD_CS_GPIO:GPIO7_A4
+ register "lcd_cs_gpio" = "0xff7e0005"
+end
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
new file mode 100644
index 0000000..349240f
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -0,0 +1,143 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/cache.h>
+#include <delay.h>
+#include <edid.h>
+#include <vbe.h>
+#include <boot/coreboot_tables.h>
+#include <device/i2c.h>
+#include <soc/rockchip/rk3288/gpio.h>
+#include <soc/rockchip/rk3288/soc.h>
+#include <soc/rockchip/rk3288/pmu.h>
+#include <soc/rockchip/rk3288/clock.h>
+#include <soc/rockchip/rk3288/spi.h>
+#include "pmic.h"
+
+#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
+#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
+#define DRAM_END (DRAM_START + DRAM_SIZE)
+
+static void setup_gpio(void)
+{
+ /*SOC and TPM reset GPIO, active high.*/
+ gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 2}, 0);
+
+ /* Configure GPIO for lcd_bl_en */
+ gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 2}, 1);
+
+ /*Configure backlight PWM 100% brightness*/
+ gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 0}, 0);
+
+ /* Configure GPIO for lcd_en */
+ gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 7}, 1);
+}
+
+static void setup_iomux(void)
+{
+ /*i2c0 for pmic*/
+ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
+ setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
+
+ /*i2c1 for tpm*/
+ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+
+ /*i2c2 for codec*/
+ writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);
+
+ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
+ writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
+ writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+ writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
+ writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
+ writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
+ writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
+ writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+}
+
+static void setup_usb_poweron(void)
+{
+ /* Configure GPIO for usb1_pwr_en */
+ gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 3}, 1);
+
+ /* Configure GPIO for usb2_pwr_en */
+ gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 4}, 1);
+
+ /* Configure GPIO for 5v_drv */
+ gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 3}, 1);
+}
+
+static void configure_sdmmc(void)
+{
+ /* Configure GPIO for sd_en */
+ gpio_output((gpio_t){.port = 7, .bank = GPIO_C, .idx = 5}, 1);
+
+ /* Configure GPIO for sd_detec */
+ gpio_input_pullup((gpio_t){.port = 7, .bank = GPIO_A, .idx = 5});
+
+ /*use sdmmc0 io, disable JTAG function*/
+ writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
+}
+
+static void configure_emmc(void)
+{
+ /* Configure GPIO for emmc_pwrctrl */
+ gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 4}, 1);
+}
+
+static void configure_i2s(void)
+{
+ /*AUDIO IO domain 1.8V voltage selection*/
+ writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+ rkclk_configure_i2s(12288000);
+}
+
+static void mainboard_init(device_t dev)
+{
+ setup_iomux();
+ pmic_init(0);
+ setup_gpio();
+ setup_usb_poweron();
+ configure_sdmmc();
+ configure_emmc();
+ configure_i2s();
+ rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+void lb_board(struct lb_header *header)
+{
+ struct lb_range *dma;
+
+ dma = (struct lb_range *)lb_new_record(header);
+ dma->tag = LB_TAB_DMA;
+ dma->size = sizeof(*dma);
+ dma->range_start = CONFIG_DRAM_DMA_START;
+ dma->range_size = CONFIG_DRAM_DMA_SIZE;
+}
diff --git a/src/mainboard/google/veyron_pinky/pmic.c b/src/mainboard/google/veyron_pinky/pmic.c
new file mode 100644
index 0000000..2e6f0ab
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/pmic.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "pmic.h"
+
+#define RK808_ADDR 0x1b
+#define LOD1EN (1 << 0)
+#define LOD2EN (1 << 1)
+#define LOD3EN (1 << 2)
+#define LOD4EN (1 << 3)
+#define LOD5EN (1 << 4)
+#define LOD6EN (1 << 5)
+#define LOD7EN (1 << 6)
+#define LOD8EN (1 << 7)
+
+#define LDO_BASE18V 18
+#define LDO_BASE08V 8
+#define LDOVSEL(mV, base) (mV/100 - base)
+
+struct rk808_reg {
+ u8 reg;
+ u8 val;
+};
+
+enum {
+ LDO_EN = 0x24,
+ LDO1_ONSEL = 0x3B,
+ LDO1_SLPSEL,
+ LDO2_ONSEL,
+ LDO2_SLPSEL,
+ LDO3_ONSEL,
+ LDO3_SLPSEL,
+ LDO4_ONSEL,
+ LDO4_SLPSEL,
+ LDO5_ONSEL,
+ LDO5_SLPSEL,
+ LDO6_ONSEL,
+ LDO6_SLPSEL,
+ LDO7_ONSEL,
+ LDO7_SLPSEL,
+ LDO8_ONSEL,
+ LDO8_SLPSEL,
+};
+
+static struct rk808_reg ldo_initlist[] = {
+ {LDO4_ONSEL, LDOVSEL(1800, LDO_BASE18V)}, /*vcc18_lcd*/
+ {LDO5_ONSEL, LDOVSEL(1800, LDO_BASE18V)}, /*vcc18_codec*/
+ {LDO6_ONSEL, LDOVSEL(1000, LDO_BASE08V)}, /*vcc10_lcd*/
+ {LDO8_ONSEL, LDOVSEL(3300, LDO_BASE18V)}, /*vccio_sd*/
+};
+
+void pmic_init(unsigned int bus)
+{
+ uint8_t read_reg;
+ int i;
+ for (i = 0; i < ARRAY_SIZE(ldo_initlist); i++) {
+ struct rk808_reg *reg = &ldo_initlist[i];
+ i2c_writeb(bus, RK808_ADDR, reg->reg, reg->val);
+ }
+
+ /*enable ldo4,ldo5,ldo6,ldo8*/
+ i2c_readb(bus, RK808_ADDR, LDO_EN, &read_reg);
+ i2c_writeb(bus, RK808_ADDR, LDO_EN, read_reg | LOD8EN | LOD6EN
+ | LOD5EN | LOD4EN);
+}
diff --git a/src/mainboard/google/veyron_pinky/pmic.h b/src/mainboard/google/veyron_pinky/pmic.h
new file mode 100644
index 0000000..dd6ed0b
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/pmic.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__
+#define __SOC_ROCKCHIP_RK3288_PMIC_H__
+void pmic_init(unsigned int bus);
+#endif
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c
new file mode 100644
index 0000000..e1062ca
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/romstage.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <armv7.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <delay.h>
+#include <program_loading.h>
+#include <timestamp.h>
+#include <arch/cache.h>
+#include <arch/exception.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/rockchip/rk3288/sdram.h>
+#include <soc/rockchip/rk3288/clock.h>
+#include "timer.h"
+
+void main(void)
+{
+#if CONFIG_COLLECT_TIMESTAMPS
+ uint64_t start_romstage_time;
+ uint64_t before_dram_time;
+ uint64_t after_dram_time;
+ uint64_t base_time = timestamp_get();
+ start_romstage_time = timestamp_get();
+#endif
+ /* used for MMU and CBMEM setup, in MB */
+ u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
+ u32 dram_size = CONFIG_DRAM_SIZE_MB;
+ u32 dram_end = dram_start + dram_size;
+
+ console_init();
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_dram_time = timestamp_get();
+#endif
+ sdram_init(get_sdram_config());
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_dram_time = timestamp_get();
+#endif
+ mmu_init();
+ /* Device memory below DRAM is uncached. */
+ mmu_config_range(0, dram_start, DCACHE_OFF);
+ /* DRAM is cached. */
+ mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+ /* A window for DMA is uncached. */
+ mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
+ CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+ /* The space above DRAM is uncached. */
+ if (dram_end < 4096)
+ mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+ dcache_mmu_enable();
+
+ setup_chromeos_gpios();
+
+ cbmem_initialize_empty();
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(base_time);
+ timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
+ timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
+ timestamp_add(TS_AFTER_INITRAM, after_dram_time);
+ timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+ run_ramstage();
+}
diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c
new file mode 100644
index 0000000..b3600fb
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/sdram_configs.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <arch/io.h>
+#include <string.h>
+#include <types.h>
+#include <console/console.h>
+#include <soc/rockchip/rk3288/sdram.h>
+#include <soc/rockchip/rk3288/gpio.h>
+
+static struct rk3288_sdram_params sdram_configs[] = {
+#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
+};
+
+#define GPIO_RAMCODE0 (gpio_t){.port = 8, .bank = GPIO_A, .idx = 0}
+#define GPIO_RAMCODE1 (gpio_t){.port = 8, .bank = GPIO_A, .idx = 1}
+#define GPIO_RAMCODE2 (gpio_t){.port = 8, .bank = GPIO_A, .idx = 2}
+#define GPIO_RAMCODE3 (gpio_t){.port = 8, .bank = GPIO_A, .idx = 3}
+
+u32 sdram_get_ram_code(void)
+{
+ u32 code = 0;
+
+ gpio_input(GPIO_RAMCODE0);
+ gpio_input(GPIO_RAMCODE1);
+ gpio_input(GPIO_RAMCODE2);
+ gpio_input(GPIO_RAMCODE3);
+
+ code = gpio_get_in_value(GPIO_RAMCODE3) << 3
+ | gpio_get_in_value(GPIO_RAMCODE2) << 2
+ | gpio_get_in_value(GPIO_RAMCODE1) << 1
+ | gpio_get_in_value(GPIO_RAMCODE0) << 0;
+
+ return code;
+}
+
+const struct rk3288_sdram_params *get_sdram_config()
+{
+ u32 ramcode = sdram_get_ram_code();
+
+ if (ramcode >= ARRAY_SIZE(sdram_configs)
+ || sdram_configs[ramcode].dramtype == UNUSED)
+ die("Invalid RAMCODE.");
+ return &sdram_configs[ramcode];
+}
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
new file mode 100644
index 0000000..409a7ca
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
@@ -0,0 +1,77 @@
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x35,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xBB,
+ .trp = 0x8,
+ .trtw = 0x4,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x6,
+ .tras = 0x14,
+ .trc = 0x1D,
+ .trcd = 0x8,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x200,
+ .txp = 0x4,
+ .txpdll = 0xD,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x6,
+ .tcksrx = 0x6,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x36,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x3AD48890,
+ .dtpr1 = 0xBB08D8,
+ .dtpr2 = 0x1002B600,
+ .mr[0] = 0x840,
+ .mr[1] = 0x40,
+ .mr[2] = 0x8,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x2891E41D,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 3,
+ .ddr_freq = 533000000,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
new file mode 100644
index 0000000..315e542
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* two Samsung K4E8E304ED-EGCE000 chips */
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ },
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x1
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 2,
+ .ddr_freq = 533000000,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc
new file mode 100644
index 0000000..06498f7
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc
@@ -0,0 +1,3 @@
+{
+ .dramtype= UNUSED
+},
\ No newline at end of file
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