[coreboot-gerrit] Patch set updated for coreboot: b45f067 add make_idb.py & update bootblock
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Mar 23 19:11:16 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8862
-gerrit
commit b45f067f3589518aa56c2de47898bf7bf3fe4ba2
Author: huang lin <hl at rock-chips.com>
Date: Tue Aug 26 17:31:28 2014 +0800
add make_idb.py & update bootblock
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: Ica7b2bf2cf649c2731933ce59a263692bb2c0282
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: ba9c36daedc749748f45e68a84f8c34c636adb1c
Original-Change-Id: Ia0e4e39d4391674f25e630b40913eb99ff3f75c4
Original-Signed-off-by: Jeffy Chen <jeffy.chen at rock-chips.com>
Original-Signed-off-by: huang lin <hl at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209427
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
Original-Commit-Queue: Julius Werner <jwerner at chromium.org>
---
src/mainboard/google/veyron/Kconfig | 4 ++
src/soc/rockchip/rk3288/Kconfig | 5 ++
src/soc/rockchip/rk3288/Makefile.inc | 10 +++
src/soc/rockchip/rk3288/bootblock.c | 8 +++
util/rockchip/make_idb.py | 124 +++++++++++++++++++++++++++++++++++
5 files changed, 151 insertions(+)
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
index bbbc617..0ae425e 100644
--- a/src/mainboard/google/veyron/Kconfig
+++ b/src/mainboard/google/veyron/Kconfig
@@ -44,6 +44,10 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 1
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 2
+
config DRAM_DMA_START
hex
default 0x10000000
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 0fadefd..5aa7f0c 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -54,6 +54,10 @@ config BOOTBLOCK_CPU_INIT
# 0xFF71_3000 CBFS mapping cache (20K)
# 0xFF71_7FFF End of iRAM.
+config SYS_SRAM_BASE
+ hex "SRAM base address"
+ default 0xFF700000
+
config SYS_SDRAM_BASE
hex "SDRAM base address"
default 0x00000000
@@ -110,6 +114,7 @@ config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0xff700000
+
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on CONSOLE_SERIAL_UART
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index e0f3224..7d5b3a5 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -17,6 +17,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+IDBTOOL = util/rockchip/make_idb.py
+
#bootblock-y += bootblock.c
bootblock-y += cbmem.c
bootblock-y += timer.c
@@ -43,3 +45,11 @@ ramstage-y += clock.c
ramstage-y += spi.c
ramstage-y += media.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+
+$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
+ cp $< $@
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+ @printf "Generating: $(subst $(obj)/,,$(@))\n"
+ @mkdir -p $(dir $@)
+ @$(IDBTOOL) --from=$< --to=$@ --enable-align
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index 04afae5..e6e0944 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -20,11 +20,19 @@
#include <console/console.h>
#include <arch/cache.h>
#include <bootblock_common.h>
+#include <arch/io.h>
#include "timer.h"
#include "clock.h"
+#include "grf.h"
+#include "spi.h"
static void bootblock_cpu_init(void)
{
+ writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
+ writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rk3288_init_timer();
+ console_init();
rkclk_init();
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
}
diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py
new file mode 100755
index 0000000..64fb804
--- /dev/null
+++ b/util/rockchip/make_idb.py
@@ -0,0 +1,124 @@
+#!/usr/bin/env python
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+import struct
+import sys
+from io import SEEK_SET, SEEK_END
+
+class IDBTool:
+ def __init__(self):
+ print "Initialize IDBTool"
+
+ def p_rc4(self, buf, length):
+ key = (124,78,3,4,85,5,9,7,45,44,123,56,23,13,23,17)
+ K = key * 16
+ S = [i for i in range(256)]
+
+ j = 0
+ for i in range(256):
+ j = (j + S[i] + K[i]) % 256
+ temp = S[i]; S[i] = S[j]; S[j] = temp;
+
+ i = j = k = 0
+ for x in range(length):
+ i = (i+1) % 256
+ j = (j + S[i]) % 256
+ temp = S[i]; S[i] = S[j]; S[j] = temp
+ k = (S[i] + S[j]) % 256
+ buf[x] = struct.pack('B', ord(buf[x]) ^ S[k])
+
+ def makeIDB(self, from_file, to_file, rc4_flag = False, align_flag = False):
+ try:
+ fin = open(from_file, 'rb')
+ except:
+ sys.exit("Failed to open file : " + from_file)
+
+ try:
+ fin.seek(0, SEEK_END)
+ if (fin.tell() > 4 * 1024 * 1024):
+ sys.exit("Input file is more than 4MB")
+ fin.seek(0)
+ data = fin.read()
+ finally:
+ fin.close()
+
+ data_len = len(data)
+ SECTOR_SIZE = 512
+ PAGE_ALIGN = 4
+ sectors = (data_len + 4 - 1) / SECTOR_SIZE + 1
+ pages = (sectors - 1) / PAGE_ALIGN + 1
+ sectors = pages * PAGE_ALIGN;
+
+ buf = [B'\0'] * sectors * SECTOR_SIZE
+ buf[:4] = "RK32"
+ buf[4 : 4+data_len] = data
+
+ idblock = [B'\0'] * 4 * SECTOR_SIZE
+ blank = [B'\0'] * 4 * SECTOR_SIZE
+ idblock[:4] = ['\x55', '\xAA', '\xF0', '\x0F']
+
+ if (not rc4_flag):
+ idblock[8:12] = struct.pack("<I", 1)
+ else:
+ for i in range(sectors):
+ list_tmp = buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)]
+ self.p_rc4(list_tmp, SECTOR_SIZE)
+ buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] = list_tmp
+
+ idblock[12:16] = struct.pack("<HH", 4, 4);
+ idblock[506:510] = struct.pack("<HH", sectors, sectors);
+ self.p_rc4(idblock, SECTOR_SIZE)
+
+ try:
+ fout = open(to_file, "wb+")
+ except:
+ sys.exit("Failed to open output file : " + to_file)
+
+ try:
+ if (align_flag):
+ fout.write(''.join(idblock))
+ fout.write(''.join(blank))
+
+ for s in xrange(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE):
+ fout.write(''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE]))
+ fout.write(''.join(blank))
+ else:
+ fout.write(''.join(idblock))
+ fout.write(''.join(buf))
+ fout.flush()
+ except:
+ sys.exit("Failed to write data to : " + to_file)
+ finally:
+ fout.close()
+ print "DONE"
+
+def usage():
+ print "Usage: make_idb.py [--enable-rc4] [--enable-align] [--to=out] --from=in"
+
+if __name__ == '__main__':
+ rc4_flag = align_flag = False
+ to_file = "IDBlock.bin"
+
+ for para in sys.argv[1:]:
+ if (para == "--enable-rc4"):
+ rc4_flag = True
+ elif (para == "--enable-align"):
+ align_flag = True
+ elif (para.startswith("--to=")):
+ to_file = para.split('=')[1]
+ elif (para.startswith("--from=")):
+ from_file = para.split('=')[1]
+ elif (para == "--help" or para == "-h"):
+ usage()
+ sys.exit()
+ else:
+ usage()
+ sys.exit()
+ if ('from_file' not in vars() or to_file == ''):
+ usage()
+ sys.exit()
+
+ idbtool = IDBTool()
+ idbtool.makeIDB(from_file, to_file, rc4_flag, align_flag)
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