[coreboot-gerrit] New patch to review for coreboot: 306b9b7 ryu: use padconfig API in bootblock

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8879

-gerrit

commit 306b9b781a5424fd49abd7df73689674a0919e40
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Aug 1 16:11:48 2014 -0500

    ryu: use padconfig API in bootblock
    
    Switch over to the padconfig API for bootblock PAD configurations.
    Aside from support code, each entry is 4 bytes. The open coded
    calls were 12 bytes each.
    
    BUG=chrome-os-partner:29981
    BRANCH=None
    TEST=Built for ryu.
    
    Change-Id: Iff981509f258c8fe7bbc2e24ce87bad0c43a55b8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8a7ee469124eeb6d05b978b5e68a2fc03b102f47
    Original-Change-Id: I2d32d702da38bc0d87a1c159113bba32f4c03407
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/210837
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
 src/mainboard/google/rush_ryu/bootblock.c | 44 +++++++++++--------------------
 1 file changed, 16 insertions(+), 28 deletions(-)

diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c
index b74baee..a9de44a 100644
--- a/src/mainboard/google/rush_ryu/bootblock.c
+++ b/src/mainboard/google/rush_ryu/bootblock.c
@@ -26,8 +26,6 @@
 #include <soc/padconfig.h>
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/nvidia/tegra132/clk_rst.h>
-#include <soc/nvidia/tegra132/gpio.h>
-#include <soc/nvidia/tegra132/pinmux.h>
 #include <soc/nvidia/tegra132/spi.h>	/* FIXME: move back to soc code? */
 
 #include "pmic.h"
@@ -67,6 +65,20 @@ static void set_clock_sources(void)
 	clock_configure_source(sbc4, PLLP, 33333);
 }
 
+static const struct pad_config padcfgs[] = {
+	/* Board build id bits 1:0 */
+	PAD_CFG_GPIO_INPUT(KB_COL4, PINMUX_PULL_NONE),
+	PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
+	/* PMIC i2C bus */
+	PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
+	PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
+	/* SPI fLash: mosi, miso, clk, cs0  */
+	PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
+	PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
+	PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4),
+	PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4),
+};
+
 void bootblock_mainboard_init(void)
 {
 	set_clock_sources();
@@ -75,35 +87,11 @@ void bootblock_mainboard_init(void)
 				 CLK_H_I2C5 | CLK_H_APBDMA,
 				 0, CLK_V_MSELECT, 0, 0);
 
-	// Board ID GPIOs, bits 0-3.
-	gpio_input(GPIO(Q3));
-	gpio_input(GPIO(T1));
-	gpio_input(GPIO(X1));
-	gpio_input(GPIO(X4));
+	/* Set up the pads required to load romstage. */
+	soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
 
-	// I2C5 (PMU) clock.
-	pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
-			  PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
-	// I2C5 (PMU) data.
-	pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
-			  PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
 	i2c_init(4);
 	pmic_init(4);
 
-	/* SPI4 data out (MOSI) */
-	pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
-			  PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
-			  PINMUX_PULL_UP);
-	/* SPI4 data in (MISO) */
-	pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
-			  PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
-			  PINMUX_PULL_UP);
-	/* SPI4 clock */
-	pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
-			  PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
-	/* SPI4 chip select 0 */
-	pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
-			  PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
-
 	tegra_spi_init(4);
 }