[coreboot-gerrit] Patch merged into coreboot/master: 31c6e63 PCIe: Add L1 Sub-State support.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 31c6e632cf607ad8364c49b934f726ef02486d46
Author: Kenji Chen <kenji.chen at intel.com>
Date:   Sat Oct 4 01:14:44 2014 +0800

    PCIe: Add L1 Sub-State support.
    
    Enable L1 Sub-State when both root port and endpoint support it.
    
    [pg: keyed the feature to MMCONF_SUPPORT, otherwise boards
    without that capability fail to build.]
    
    Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092
    Original-BUG=chrome-os-partner:31424
    Original-TEST=Build a image and run on Samus proto boards to check if the
    settings are applied correctly. I just only have proto boards and
    need someone having EVT boards to confirm the settings.
    Original-Signed-off-by: Kenji Chen <kenji.chen at intel.com>
    Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a
    Original-Reviewed-on: https://chromium-review.googlesource.com/221436
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/8832
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/8832 for details.

-gerrit