[coreboot-gerrit] Patch set updated for coreboot: 55fc764 imgtec/danube: Add support for ImgTec Danube SoC
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Sat Mar 21 14:10:47 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8762
-gerrit
commit 55fc76484043242a1ca9e573205898ba3516c53c
Author: Paul Burton <paul.burton at imgtec.com>
Date: Sat Jun 14 00:08:02 2014 +0100
imgtec/danube: Add support for ImgTec Danube SoC
Add build infrastructure and basic support code for the ImgTec Danube
SoC. This support is sufficient to run on a simulator.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I59e36589765bf06b075fd4850215a0ef71246bb1
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 881278d7fbb8e6803bc8f6f9e84c64640b097401
Original-Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958
Original-Signed-off-by: Paul Burton <paul.burton at imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207974
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/cpu/Makefile.inc | 1 +
src/soc/Kconfig | 1 +
src/soc/Makefile.inc | 1 +
src/soc/imgtec/Kconfig | 1 +
src/soc/imgtec/Makefile.inc | 1 +
src/soc/imgtec/danube/Kconfig | 69 ++++++++++++
src/soc/imgtec/danube/Makefile.inc | 40 +++++++
src/soc/imgtec/danube/bootblock.c | 24 ++++
src/soc/imgtec/danube/cbmem.c | 29 +++++
src/soc/imgtec/danube/uart.c | 217 +++++++++++++++++++++++++++++++++++++
10 files changed, 384 insertions(+)
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 2411aeb..da0e76f 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -5,6 +5,7 @@ subdirs-y += allwinner
subdirs-y += amd
subdirs-y += dmp
subdirs-y += armltd
+subdirs-y += imgtec
subdirs-y += intel
subdirs-y += ti
subdirs-y += via
diff --git a/src/soc/Kconfig b/src/soc/Kconfig
index a36bedd..43c2010 100644
--- a/src/soc/Kconfig
+++ b/src/soc/Kconfig
@@ -1,3 +1,4 @@
+source src/soc/imgtec/Kconfig
source src/soc/intel/Kconfig
source src/soc/nvidia/Kconfig
source src/soc/qualcomm/Kconfig
diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc
index 80dd109..543e155 100644
--- a/src/soc/Makefile.inc
+++ b/src/soc/Makefile.inc
@@ -1,6 +1,7 @@
################################################################################
## Subdirectories
################################################################################
+subdirs-y += imgtec
subdirs-y += intel
subdirs-y += nvidia
subdirs-y += qualcomm
diff --git a/src/soc/imgtec/Kconfig b/src/soc/imgtec/Kconfig
new file mode 100644
index 0000000..4364a94
--- /dev/null
+++ b/src/soc/imgtec/Kconfig
@@ -0,0 +1 @@
+source src/soc/imgtec/danube/Kconfig
diff --git a/src/soc/imgtec/Makefile.inc b/src/soc/imgtec/Makefile.inc
new file mode 100644
index 0000000..06ce1d2
--- /dev/null
+++ b/src/soc/imgtec/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_CPU_IMGTEC_DANUBE) += danube
diff --git a/src/soc/imgtec/danube/Kconfig b/src/soc/imgtec/danube/Kconfig
new file mode 100644
index 0000000..df2b685
--- /dev/null
+++ b/src/soc/imgtec/danube/Kconfig
@@ -0,0 +1,69 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+config CPU_IMGTEC_DANUBE
+ select CPU_MIPS32R2
+ select DYNAMIC_CBMEM
+ select HAVE_UART_MEMORY_MAPPED
+ select HAVE_UART_SPECIAL
+ bool
+
+if CPU_IMGTEC_DANUBE
+
+config BOOTBLOCK_CPU_INIT
+ string
+ default "soc/imgtec/danube/bootblock.c"
+
+config BOOTBLOCK_BASE
+ hex
+ default 0x9b000000
+
+config CBFS_ROM_OFFSET
+ # Effectively the maximum size of the bootblock
+ hex
+ default 0x4000
+
+config ROMSTAGE_BASE
+ hex
+ default 0x9b004000
+ help
+ The address where romstage is supposed to be loaded, right above the
+ bootblock.
+
+config CBMEM_CONSOLE_PRERAM_BASE
+ hex "memory address of the CBMEM console buffer"
+ default 0x9b00f800
+ help
+ Allocate 4KB to the pre-ram console buffer, we should be able to use
+ GRAM eventually and have a much larger buffer.
+
+config STACK_TOP
+ hex
+ default CBMEM_CONSOLE_PRERAM_BASE
+
+config STACK_BOTTOM
+ hex
+ default 0x9b00f000
+ help
+ Allocating 12KB for the stack, should be able to have more once GRAM
+ is available.
+
+endif
diff --git a/src/soc/imgtec/danube/Makefile.inc b/src/soc/imgtec/danube/Makefile.inc
new file mode 100644
index 0000000..74822de
--- /dev/null
+++ b/src/soc/imgtec/danube/Makefile.inc
@@ -0,0 +1,40 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y)
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
+romstage-y += uart.c
+ramstage-y += uart.c
+endif
+
+romstage-y += cbmem.c
+ramstage-y += cbmem.c
+
+# Generate the actual coreboot bootblock code
+$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
+ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
+ $(OBJCOPY_bootblock) -O binary $< $@.tmp
+ @mv $@.tmp $@
+
+# Create a complete bootblock which will start up the system
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+ @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n"
+ $(BIMGTOOL) $< $@ $(CONFIG_BOOTBLOCK_BASE)
diff --git a/src/soc/imgtec/danube/bootblock.c b/src/soc/imgtec/danube/bootblock.c
new file mode 100644
index 0000000..f6cc76b
--- /dev/null
+++ b/src/soc/imgtec/danube/bootblock.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+static void bootblock_cpu_init(void)
+{
+}
diff --git a/src/soc/imgtec/danube/cbmem.c b/src/soc/imgtec/danube/cbmem.c
new file mode 100644
index 0000000..5fb6c0e
--- /dev/null
+++ b/src/soc/imgtec/danube/cbmem.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <stdlib.h>
+
+void *cbmem_top(void)
+{
+ uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20;
+ return (void *)(top + CONFIG_SYS_SDRAM_BASE);
+}
diff --git a/src/soc/imgtec/danube/uart.c b/src/soc/imgtec/danube/uart.c
new file mode 100644
index 0000000..855fce5
--- /dev/null
+++ b/src/soc/imgtec/danube/uart.c
@@ -0,0 +1,217 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <uart.h>
+#include <uart8250.h>
+
+/* Should support 8250, 16450, 16550, 16550A type UARTs */
+
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ */
+#define SINGLE_CHAR_TIMEOUT (50 * 1000)
+#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
+#define UART_SHIFT 2
+
+#define GEN_ACCESSOR(name, idx) \
+static inline uint8_t read_##name(unsigned base_port) \
+{ \
+ return read8(base_port + (idx << UART_SHIFT)); \
+} \
+ \
+static inline void write_##name(unsigned base_port, uint8_t val) \
+{ \
+ write8(base_port + (idx << UART_SHIFT), val); \
+}
+
+GEN_ACCESSOR(rbr, UART8250_RBR)
+GEN_ACCESSOR(tbr, UART8250_TBR)
+GEN_ACCESSOR(ier, UART8250_IER)
+GEN_ACCESSOR(fcr, UART8250_FCR)
+GEN_ACCESSOR(lcr, UART8250_LCR)
+GEN_ACCESSOR(mcr, UART8250_MCR)
+GEN_ACCESSOR(lsr, UART8250_LSR)
+GEN_ACCESSOR(dll, UART8250_DLL)
+GEN_ACCESSOR(dlm, UART8250_DLM)
+
+static int uart8250_mem_can_tx_byte(unsigned base_port)
+{
+ return read_lsr(base_port) & UART8250_LSR_THRE;
+}
+
+static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while (i-- && !uart8250_mem_can_tx_byte(base_port))
+ udelay(1);
+ write_tbr(base_port, data);
+}
+
+static void uart8250_mem_tx_flush(unsigned base_port)
+{
+ unsigned long int i = FIFO_TIMEOUT;
+ while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT))
+ udelay(1);
+}
+
+static int uart8250_mem_can_rx_byte(unsigned base_port)
+{
+ return read_lsr(base_port) & UART8250_LSR_DR;
+}
+
+static unsigned char uart8250_mem_rx_byte(unsigned base_port)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while (i-- && !uart8250_mem_can_rx_byte(base_port))
+ udelay(1);
+ if (i)
+ return read_rbr(base_port);
+ else
+ return 0x0;
+}
+
+static void uart8250_mem_init(unsigned base_port, unsigned divisor)
+{
+ /* Disable interrupts */
+ write_ier(base_port, 0x0);
+ /* Enable FIFOs */
+ write_fcr(base_port, UART8250_FCR_FIFO_EN);
+
+ /* Assert DTR and RTS so the other end is happy */
+ write_mcr(base_port, UART8250_MCR_DTR | UART8250_MCR_RTS);
+
+ /* DLAB on */
+ write_lcr(base_port, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS);
+
+ write_dll(base_port, divisor & 0xFF);
+ write_dlm(base_port, (divisor >> 8) & 0xFF);
+
+ /* Set to 3 for 8N1 */
+ write_lcr(base_port, CONFIG_TTYS0_LCS);
+}
+
+static unsigned int uart_platform_refclk(void)
+{
+ /* TODO: this is entirely arbitrary */
+ return 1000000;
+}
+
+static unsigned int uart_platform_base(int idx)
+{
+ switch (idx) {
+ case 0:
+ return 0xb8101400;
+
+ case 1:
+ return 0xb8101500;
+
+ default:
+ return 0x0;
+ }
+}
+
+/* Calculate divisor. Do not floor but round to nearest integer. */
+static unsigned int uart_baudrate_divisor(unsigned int baudrate,
+ unsigned int refclk, unsigned int oversample)
+{
+ return (1 + (2 * refclk) / (baudrate * oversample)) / 2;
+}
+
+static void danube_uart_init(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+
+ unsigned int div;
+ div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,
+ uart_platform_refclk(), 16);
+ uart8250_mem_init(base, div);
+}
+
+static void danube_uart_tx_byte(unsigned char data)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+ uart8250_mem_tx_byte(base, data);
+}
+
+static unsigned char danube_uart_rx_byte(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return 0xff;
+ return uart8250_mem_rx_byte(base);
+}
+
+static void danube_uart_tx_flush(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+ uart8250_mem_tx_flush(base);
+}
+
+#if !defined(__PRE_RAM__)
+
+static const struct console_driver danube_uart_console __console = {
+ .init = danube_uart_init,
+ .tx_byte = danube_uart_tx_byte,
+ .tx_flush = danube_uart_tx_flush,
+ .rx_byte = danube_uart_rx_byte,
+};
+
+uint32_t uartmem_getbaseaddr(void)
+{
+ return uart_platform_base(0);
+}
+
+#else /* __PRE_RAM__ */
+
+void uart_init(void)
+{
+ danube_uart_init();
+}
+
+void uart_tx_byte(unsigned char data)
+{
+ danube_uart_tx_byte(data);
+}
+
+unsigned char uart_rx_byte(void)
+{
+ return danube_uart_rx_byte();
+}
+
+void uart_tx_flush(void)
+{
+ danube_uart_tx_flush();
+}
+
+#endif /* __PRE_RAM__ */
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