[coreboot-gerrit] Patch set updated for coreboot: e3c741b danube: use SOC specific rom stage code

Patrick Georgi (pgeorgi@google.com) gerrit at coreboot.org
Sat Mar 21 14:09:41 CET 2015


Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8764

-gerrit

commit e3c741bb4b7e8aae7e5e3d0d7ee98dad7a04ef3a
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Sep 2 13:20:47 2014 -0700

    danube: use SOC specific rom stage code
    
    Romstage initialization code does not need to be board specific, keep
    it in the SOC directory. Should there be a need for the board specific
    code, it can be added later.
    
    BUG=chrome-os-partner:31438
    TEST=with upcoming patches, the urara board coreboot builds fine
    
    Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3
    Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/215992
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/imgtec/danube/Makefile.inc |  1 +
 src/soc/imgtec/danube/romstage.c   | 39 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/src/soc/imgtec/danube/Makefile.inc b/src/soc/imgtec/danube/Makefile.inc
index d7628ed..6a2ba4f 100644
--- a/src/soc/imgtec/danube/Makefile.inc
+++ b/src/soc/imgtec/danube/Makefile.inc
@@ -36,6 +36,7 @@ ramstage-y += cbmem.c
 ramstage-y += timestamp.c
 
 romstage-y += cbmem.c
+romstage-y += romstage.c
 romstage-y += timestamp.c
 
 # Generate the actual coreboot bootblock code
diff --git a/src/soc/imgtec/danube/romstage.c b/src/soc/imgtec/danube/romstage.c
new file mode 100644
index 0000000..53ca898
--- /dev/null
+++ b/src/soc/imgtec/danube/romstage.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/stages.h>
+#include <cbfs.h>
+#include <console/console.h>
+
+void main(void)
+{
+	void *entry;
+
+	console_init();
+
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+				CONFIG_CBFS_PREFIX "/ramstage");
+	if (entry != (void *)-1)
+		stage_exit(entry);
+
+	hlt();
+}



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