[coreboot-gerrit] Patch set updated for coreboot: f3de724 tegra132: implement platform_prog_run()

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8848

-gerrit

commit f3de724bb8ecf37c3291da5606eb3f3955320992
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Mar 20 16:47:21 2015 -0500

    tegra132: implement platform_prog_run()
    
    The tegra132 SoC is currently booting up on the AVP cpu which
    bootstraps the rest of the SoC. Upon exiting romstage it
    runs ramstage from its faster armv8 core. Instead of hard
    coding the stage loading operations use run_ramstage().
    
    Change-Id: Ib9b3eecf376ae022f910295920a085bde6e17f9f
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/nvidia/tegra132/romstage.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 812d147..b70478e 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -23,6 +23,7 @@
 #include <console/cbmem_console.h>
 #include <console/console.h>
 #include <arch/exception.h>
+#include <program_loading.h>
 
 #include <soc/addressmap.h>
 #include <soc/sdram_configs.h>
@@ -34,8 +35,6 @@
 void romstage(void);
 void romstage(void)
 {
-	void *entry;
-
 	console_init();
 	exception_init();
 
@@ -66,12 +65,14 @@ void romstage(void)
 	ccplex_load_mts();
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-				CONFIG_CBFS_PREFIX "/ramstage");
-
 	cbmemc_reinit();
 
-	ccplex_cpu_start(entry);
+	run_ramstage();
+}
+
+void platform_prog_run(struct prog *prog)
+{
+	ccplex_cpu_start(prog_entry(prog));
 
 	clock_halt_avp();
 }