[coreboot-gerrit] Patch set updated for coreboot: 502e9f8 tegra124: implement platform_prog_run()

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8847

-gerrit

commit 502e9f89dd3c690f365c693b3f451d698ae3f16d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Mar 20 16:42:17 2015 -0500

    tegra124: implement platform_prog_run()
    
    The tegra124 SoC is currently booting up on the AVP cpu which
    bootstraps the rest of the SoC. Upon exiting bootblock it
    runs romstage from its faster armv7 core. Instead of hard
    coding the stage loading operations use run_romstage().
    
    Change-Id: Idddcfd5443f08d4dd41e1d9b71650ff6d4b14bc4
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/nvidia/tegra124/bootblock.c | 37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index aec9145..0269731 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -22,16 +22,30 @@
 #include <bootblock_common.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <program_loading.h>
 #include <soc/clock.h>
 #include <soc/nvidia/tegra/apbmisc.h>
 #include "pinmux.h"
 #include "power.h"
 #include "verstage.h"
 
-void main(void)
+static void run_next_stage(void *entry)
 {
-	void *entry;
+	ASSERT(entry);
+	clock_cpu0_config(entry);
+
+	power_enable_and_ungate_cpu();
+
+	/* Repair ram on cluster0 and cluster1 after CPU is powered on. */
+	ram_repair();
+
+	clock_cpu0_remove_reset();
 
+	clock_halt_avp();
+}
+
+void main(void)
+{
 	// enable pinmux clamp inputs
 	clamp_tristate_inputs();
 
@@ -71,19 +85,12 @@ void main(void)
 			  PINMUX_INPUT_ENABLE);
 
 	if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE))
-		entry = (void *)verstage_vboot_main;
-	else
-		entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");
-
-	ASSERT(entry);
-	clock_cpu0_config(entry);
+		run_next_stage((void *)verstage_vboot_main);
 
-	power_enable_and_ungate_cpu();
-
-	/* Repair ram on cluster0 and cluster1 after CPU is powered on. */
-	ram_repair();
-
-	clock_cpu0_remove_reset();
+	run_romstage();
+}
 
-	clock_halt_avp();
+void platform_prog_run(struct prog *prog)
+{
+	run_next_stage(prog_entry(prog));
 }