[coreboot-gerrit] Patch set updated for coreboot: 286dddf mainboards/amd/fam10: Add romstage timestamps
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Fri Mar 20 21:56:00 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8776
-gerrit
commit 286dddfeba70cc5562e5192d04ef4768a6cb6bd5
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Thu Mar 19 16:44:46 2015 -0500
mainboards/amd/fam10: Add romstage timestamps
Example output:
1:start of rom stage 542
2:before ram initialization 193,989 (193,447)
3:after ram initialization 3,319,114 (3,125,124)
4:end of romstage 3,320,004 (889)
Change-Id: Idcde7dc4c7a1d6c3118c82b67e8c2fcd4a07553b
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/mainboard/advansus/a785e-i/romstage.c | 9 +++++++++
src/mainboard/amd/bimini_fam10/romstage.c | 9 +++++++++
src/mainboard/amd/mahogany_fam10/romstage.c | 9 +++++++++
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 9 +++++++++
src/mainboard/amd/tilapia_fam10/romstage.c | 9 +++++++++
src/mainboard/asus/kfsn4-dre/romstage.c | 9 +++++++++
src/mainboard/asus/m4a78-em/romstage.c | 9 +++++++++
src/mainboard/asus/m4a785-m/romstage.c | 9 +++++++++
src/mainboard/asus/m5a88-v/romstage.c | 9 +++++++++
src/mainboard/avalue/eax-785e/romstage.c | 9 +++++++++
src/mainboard/gigabyte/ma785gm/romstage.c | 9 +++++++++
src/mainboard/gigabyte/ma785gmt/romstage.c | 9 +++++++++
src/mainboard/gigabyte/ma78gm/romstage.c | 9 +++++++++
src/mainboard/hp/dl165_g6_fam10/romstage.c | 9 +++++++++
src/mainboard/iei/kino-780am2-fam10/romstage.c | 9 +++++++++
src/mainboard/jetway/pa78vm5/romstage.c | 9 +++++++++
src/mainboard/msi/ms9652_fam10/romstage.c | 9 +++++++++
src/mainboard/supermicro/h8dmr_fam10/romstage.c | 9 +++++++++
src/mainboard/supermicro/h8qme_fam10/romstage.c | 8 ++++++++
src/mainboard/supermicro/h8scm_fam10/romstage.c | 9 +++++++++
src/mainboard/tyan/s2912_fam10/romstage.c | 9 +++++++++
21 files changed, 188 insertions(+)
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index c1c9a1b..a70c269 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -34,6 +34,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -79,6 +80,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -217,6 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 6d03685..f4df3a3 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -74,6 +75,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -196,8 +200,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -216,6 +223,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb800_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index e53c64d..501c8c3 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -77,6 +78,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index ef15e83..2932c83 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/amd/amd8111/early_smbus.c"
#include <northbridge/amd/amdfam10/raminit.h>
@@ -188,6 +189,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -310,8 +314,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -324,6 +331,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 7d2f272..97bf51a 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -77,6 +78,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index 44864f6..af6858f 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -35,6 +35,7 @@ unsigned int get_sbdn(unsigned bus);
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
@@ -213,6 +214,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -341,8 +345,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -368,6 +375,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Restore default SuperIO access */
outb(0xaa, port);
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 47b9c83..da63c66 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -200,8 +204,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -217,6 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 7ebec29..e0c132f 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -200,8 +204,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -217,6 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 2339478..cc4d04d 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -34,6 +34,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -195,8 +199,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -214,6 +221,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index c1dbaa7..5cc9fb1 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -34,6 +34,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -80,6 +81,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -199,8 +203,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -218,6 +225,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 7b0168d..991531d 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -29,6 +29,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -74,6 +75,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -195,8 +199,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -212,6 +219,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index d0d6c94..a022a20 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -29,6 +29,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -74,6 +75,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -195,8 +199,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -212,6 +219,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 8861ab6..7675e25 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 4aefcd2..bf054d5 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -37,6 +37,7 @@
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include <northbridge/amd/amdfam10/raminit.h>
@@ -96,6 +97,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -202,13 +206,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synchronize FID/VID
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
bcm5785_early_setup();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram();
}
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 991cd55..5f99df6 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -77,6 +78,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index df30a69..1686988 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -34,6 +34,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -82,6 +83,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -203,8 +207,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("Die Before MCT init.");
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -220,6 +227,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 0bdcd38..b2bfc8b 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -30,6 +30,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
@@ -106,6 +107,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u8 reg;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -229,11 +233,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 4615465..980437b 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -30,6 +30,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
@@ -106,6 +107,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -226,11 +230,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
post_code(0x42); // Should never see this post code.
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index c8ed2df..20522e1 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -30,6 +30,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
@@ -171,6 +172,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -290,11 +294,15 @@ post_code(0x3D);
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x42); // Should never see this post code.
}
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 4c6292f..355cf82 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -79,6 +80,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -210,8 +214,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -230,6 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sr5650_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 7dcca17..933d709 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -30,6 +30,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
@@ -111,6 +112,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -225,11 +229,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
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