[coreboot-gerrit] New patch to review for coreboot: b394a79 PCIe: Revise L1 Sub-State support

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8833

-gerrit

commit b394a79565f40f183dfb897784ea5e1eba522ad0
Author: Kenji Chen <kenji.chen at intel.com>
Date:   Fri Jan 30 13:57:42 2015 +0800

    PCIe: Revise L1 Sub-State support
    
    BRANCH=None
    BUG=None
    TEST=Confirmed build pass only
    Signed-off-by: Kenji Chen <kenji.chen at intel.com>
    
    Change-Id: Ic0e845436614e63ad5ace7fb74400f7ea295571c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d3670b92e40d8757a48add6116a0edcec18074d8
    Original-Change-Id: I5e029b0f82a771149d4c6127e30b9062e8eaba89
    Original-Reviewed-on: https://chromium-review.googlesource.com/244514
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Commit-Queue: Kenji Chen <kenji.chen at intel.com>
    Original-Tested-by: Kenji Chen <kenji.chen at intel.com>
---
 src/device/pciexp_device.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 002a897..5f38d96 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -239,20 +239,17 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev,
 	pcie_update_cfg(root, root_cap + 0x08, ~0xe3ff0000,
 		(1 << 21) | (1 << 23) | (1 << 30));
 
-	pcie_update_cfg(root, root_cap + 0x08, ~0xf,
+	pcie_update_cfg(root, root_cap + 0x08, ~0x1f,
 		L1SubStateSupport);
 
 	for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
-		pcie_update_cfg(dev_t, end_cap + 0x08, ~0xff00,
-			(comm_mode_rst_time << 8));
-
 		pcie_update_cfg(dev_t, end_cap + 0x0c , 0xffffff04,
 			(endp_power_on_value << 3) | (power_on_scale));
 
 		pcie_update_cfg(dev_t, end_cap + 0x08, ~0xe3ff0000,
 			(1 << 21) | (1 << 23) | (1 << 30));
 
-		pcie_update_cfg(dev_t, end_cap + 0x08, ~0xf,
+		pcie_update_cfg(dev_t, end_cap + 0x08, ~0x1f,
 			L1SubStateSupport);
 
 		pciexp_enable_ltr(dev_t);