[coreboot-gerrit] New patch to review for coreboot: 6f4b541 libpayload: mips: add SOC CPU frequency; correct platform ID

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8745

-gerrit

commit 6f4b541bc447477c87ebce676b37fcae98639dcb
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Mon Jan 19 02:41:49 2015 +0000

    libpayload: mips: add SOC CPU frequency; correct platform ID
    
    Add CPU frequency corrsponding to SOC.
    Corrected platform ID.
    
    BUG=chrome-os-partner:31438
    TEST=tested on Pistachio bring up board; behaves as expected.
    BRANCH=none
    
    Change-Id: I8e5ac80e95b5169102eaa075bc22045c0789d486
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604
    Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/241427
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 payloads/libpayload/arch/mips/timer.c       | 21 +++++++++++++++++----
 payloads/libpayload/include/mips/arch/cpu.h | 11 +++++++++--
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/payloads/libpayload/arch/mips/timer.c b/payloads/libpayload/arch/mips/timer.c
index 1710a32..782959b 100644
--- a/payloads/libpayload/arch/mips/timer.c
+++ b/payloads/libpayload/arch/mips/timer.c
@@ -19,6 +19,10 @@
 
 #include <libpayload.h>
 #include <arch/cpu.h>
+#include <arch/io.h>
+
+#define PISTACHIO_CLOCK_SWITCH		0xB8144200
+#define MIPS_EXTERN_PLL_BYPASS_MASK	0x00000002
 
 /**
  * @ingroup arch
@@ -34,10 +38,19 @@ u32 cpu_khz;
 unsigned int get_cpu_speed(void)
 {
 	if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
-		cpu_khz = 50000U; /* FPGA board */
-	/* else {
-	 * TODO find CPU frequency on the real SOC
-	} */
+		cpu_khz = 50000; /* FPGA board */
+	else {
+		/* If MIPS PLL external bypass bit is set, it means
+		 * that the MIPS PLL is already set up to work at a
+		 * frequency of 550 MHz; otherwise, the crystal is
+		 * used with a frequency of 52 MHz
+		 */
+		if (read32(PISTACHIO_CLOCK_SWITCH) &
+				MIPS_EXTERN_PLL_BYPASS_MASK)
+			cpu_khz = 550000;
+		else
+			cpu_khz = 52000;
+	}
 
 	return cpu_khz;
 }
diff --git a/payloads/libpayload/include/mips/arch/cpu.h b/payloads/libpayload/include/mips/arch/cpu.h
index 952ec7c..93e42ea 100644
--- a/payloads/libpayload/include/mips/arch/cpu.h
+++ b/payloads/libpayload/include/mips/arch/cpu.h
@@ -22,8 +22,15 @@
  * Reading at this address allows to identify the platform the code is running
  * on
  */
-#define IMG_PLATFORM_ID()		(*((unsigned *)0xB8149060))
-#define IMG_PLATFORM_ID_SILICON		0xF00D0006
+
+/*
+ * This register holds the FPGA image version
+ * If we're not working on the FPGA this will be 0
+ */
+#define PRIMARY_FPGA_VERSION		0xB8149060
+#define IMG_PLATFORM_ID()		read32(PRIMARY_FPGA_VERSION)
+#define IMG_PLATFORM_ID_FPGA		0xD1400003 /* Last FPGA image */
+#define IMG_PLATFORM_ID_SILICON		0
 
 #define CP0_COUNT	9
 #define CP0_COMPARE	11