[coreboot-gerrit] Patch set updated for coreboot: c10a6e6 t132: Add support for tpm i2c

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8715

-gerrit

commit c10a6e6c3e8f49d49c9f2437fc7bba2dd4fa028e
Author: Furquan Shaikh <furquan at google.com>
Date:   Fri Jul 25 14:52:57 2014 -0700

    t132: Add support for tpm i2c
    
    Iniitialize I2C bus required for TPM operation. Problem observed was that if
    frequency is raised above 20KHz, TPM starts responding with NAKs either for
    address or for data. Need to look into that.
    
    BUG=None
    BRANCH=None
    TEST=Compiles successfully and TPM success messages seen while booting.
    
    Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/210001
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2
---
 src/mainboard/google/rush/romstage.c           | 32 ++++++++++++++++++++++++++
 src/mainboard/google/rush_ryu/romstage.c       |  4 ++++
 src/soc/nvidia/tegra132/include/soc/romstage.h |  1 +
 src/soc/nvidia/tegra132/romstage.c             |  3 +++
 4 files changed, 40 insertions(+)

diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index bb173c0..7c01a30 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -19,6 +19,38 @@
 
 #include <soc/romstage.h>
 
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra132/pinmux.h>
+#include <soc/nvidia/tegra132/gpio.h>
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void configure_tpm_i2c_bus(void)
+{
+	clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
+
+	i2c_init(2);
+}
+
+void mainboard_init_tpm_i2c(void)
+{
+	clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
+
+	gpio_output(GPIO(I5), 1);
+
+	// I2C3 (cam) clock.
+	pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
+			  PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+	// I2C3 (cam) data.
+	pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
+			  PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+
+
+	configure_tpm_i2c_bus();
+}
+
 void mainboard_configure_pmc(void)
 {
 }
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index bb173c0..9a41247 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -19,6 +19,10 @@
 
 #include <soc/romstage.h>
 
+void mainboard_init_tpm_i2c(void)
+{
+}
+
 void mainboard_configure_pmc(void)
 {
 }
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h
index f9eac26..f669121 100644
--- a/src/soc/nvidia/tegra132/include/soc/romstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/romstage.h
@@ -22,5 +22,6 @@
 
 void mainboard_configure_pmc(void);
 void mainboard_enable_vdd_cpu(void);
+void mainboard_init_tpm_i2c(void);
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 812d147..69271f0 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -30,6 +30,7 @@
 #include "ccplex.h"
 
 #include <soc/clock.h>
+#include <soc/romstage.h>
 
 void romstage(void);
 void romstage(void)
@@ -66,6 +67,8 @@ void romstage(void)
 	ccplex_load_mts();
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
+	mainboard_init_tpm_i2c();
+
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
 				CONFIG_CBFS_PREFIX "/ramstage");