[coreboot-gerrit] Patch set updated for coreboot: aab72c1 southbridge/amd/pi: Enable early I/O decode to LPC

[Dave Frodin (dave.frodin@se-eng.com)]

Dave Frodin (dave.frodin at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8661

-gerrit

commit aab72c1fb62f7f208de7c743642cf1e067721f9a
Author: Dave Frodin <dave.frodin at se-eng.com>
Date:   Fri Mar 13 08:22:17 2015 -0600

    southbridge/amd/pi: Enable early I/O decode to LPC
    
    The decode of UART addresses down to the LPC bus needs
    to occur early to allow romstage console messages to
    be seen. This enables the decode of most of the I/O
    ports typically seen in a system.
    
    Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
    Signed-off-by: Dave Frodin <dave.frodin at se-eng.com>
---
 src/southbridge/amd/pi/hudson/early_setup.c | 24 ++++++++++++++++++++
 src/southbridge/amd/pi/hudson/hudson.h      | 35 +++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 9500d0e..08697b9 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -28,6 +28,7 @@
 #include <arch/cpu.h>
 #include <cbmem.h>
 #include "hudson.h"
+#include "pci_devs.h"
 
 void hudson_pci_port80(void)
 {
@@ -93,6 +94,29 @@ void hudson_lpc_port80(void)
 	pci_write_config8(dev, 0x4a, byte);
 }
 
+void hudson_lpc_decode(void)
+{
+	device_t dev;
+	u32 tmp = 0;
+
+	/* Enable I/O decode to LPC bus */
+	dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+	tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
+		| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
+		| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
+		| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
+		| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
+		| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
+		| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
+		| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
+		| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
+		| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
+		| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
+		| DECODE_ENABLE_ADLIB_PORT;
+
+	pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp);
+}
+
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
 	int i;
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 90c3205..6cd0f78 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -55,6 +55,40 @@
 #define SPI_ROM_ENABLE                0x02
 #define SPI_BASE_ADDRESS              0xFEC10000
 
+#define LPC_IO_PORT_DECODE_ENABLE     0x44
+#define DECODE_ENABLE_PARALLEL_PORT0  (1 << 0)
+#define DECODE_ENABLE_PARALLEL_PORT1  (1 << 1)
+#define DECODE_ENABLE_PARALLEL_PORT2  (1 << 2)
+#define DECODE_ENABLE_PARALLEL_PORT3  (1 << 3)
+#define DECODE_ENABLE_PARALLEL_PORT4  (1 << 4)
+#define DECODE_ENABLE_PARALLEL_PORT5  (1 << 5)
+#define DECODE_ENABLE_SERIAL_PORT0    (1 << 6)
+#define DECODE_ENABLE_SERIAL_PORT1    (1 << 7)
+#define DECODE_ENABLE_SERIAL_PORT2    (1 << 8)
+#define DECODE_ENABLE_SERIAL_PORT3    (1 << 9)
+#define DECODE_ENABLE_SERIAL_PORT4    (1 << 10)
+#define DECODE_ENABLE_SERIAL_PORT5    (1 << 11)
+#define DECODE_ENABLE_SERIAL_PORT6    (1 << 12)
+#define DECODE_ENABLE_SERIAL_PORT7    (1 << 13)
+#define DECODE_ENABLE_AUDIO_PORT0     (1 << 14)
+#define DECODE_ENABLE_AUDIO_PORT1     (1 << 15)
+#define DECODE_ENABLE_AUDIO_PORT2     (1 << 16)
+#define DECODE_ENABLE_AUDIO_PORT3     (1 << 17)
+#define DECODE_ENABLE_MIDI_PORT0      (1 << 18)
+#define DECODE_ENABLE_MIDI_PORT1      (1 << 19)
+#define DECODE_ENABLE_MIDI_PORT2      (1 << 20)
+#define DECODE_ENABLE_MIDI_PORT3      (1 << 21)
+#define DECODE_ENABLE_MSS_PORT0       (1 << 22)
+#define DECODE_ENABLE_MSS_PORT1       (1 << 23)
+#define DECODE_ENABLE_MSS_PORT2       (1 << 24)
+#define DECODE_ENABLE_MSS_PORT3       (1 << 25)
+#define DECODE_ENABLE_FDC_PORT0       (1 << 26)
+#define DECODE_ENABLE_FDC_PORT1       (1 << 27)
+#define DECODE_ENABLE_GAME_PORT       (1 << 28)
+#define DECODE_ENABLE_KBC_PORT        (1 << 29)
+#define DECODE_ENABLE_ACPIUC_PORT     (1 << 30)
+#define DECODE_ENABLE_ADLIB_PORT      (1 << 31)
+
 static inline int hudson_sata_enable(void)
 {
 	/* True if IDE or AHCI. */
@@ -76,6 +110,7 @@ u16 pm_read16(u16 reg);
 
 #ifdef __PRE_RAM__
 void hudson_lpc_port80(void);
+void hudson_lpc_decode(void);
 void hudson_pci_port80(void);
 void hudson_clk_output_48Mhz(void);