[coreboot-gerrit] Patch set updated for coreboot: 8ae18a0 southbridge/amd/pi: Enable early I/O decode to LPC

[Dave Frodin (dave.frodin@se-eng.com)]

Dave Frodin (dave.frodin at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8661

-gerrit

commit 8ae18a036fe2fd787355615ff801b20e24a99446
Author: Dave Frodin <dave.frodin at se-eng.com>
Date:   Fri Mar 13 08:22:17 2015 -0600

    southbridge/amd/pi: Enable early I/O decode to LPC
    
    The decode of UART addresses down to the LPC bus needs
    to occur early to allow romstage console messages to
    be seen.
    
    Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
    Signed-off-by: Dave Frodin <dave.frodin at se-eng.com>
---
 src/southbridge/amd/pi/hudson/early_setup.c | 9 +++++++++
 src/southbridge/amd/pi/hudson/hudson.h      | 1 +
 2 files changed, 10 insertions(+)

diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 9500d0e..af3240b 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -93,6 +93,15 @@ void hudson_lpc_port80(void)
 	pci_write_config8(dev, 0x4a, byte);
 }
 
+void hudson_lpc_decode(void)
+{
+	device_t dev;
+
+	/* Enable I/O decode to LPC bus */
+	dev = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev, 0x44, 0xFF03FFD5);
+}
+
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
 	int i;
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 90c3205..6116713 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -76,6 +76,7 @@ u16 pm_read16(u16 reg);
 
 #ifdef __PRE_RAM__
 void hudson_lpc_port80(void);
+void hudson_lpc_decode(void);
 void hudson_pci_port80(void);
 void hudson_clk_output_48Mhz(void);