[coreboot-gerrit] Patch merged into coreboot/master: 01dde90 armv8: correct dcache line size calculation

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 01dde90eb9c070018fc11b007159c8d130b2809d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 17 13:08:06 2014 -0500

    armv8: correct dcache line size calculation
    
    The CCSIDR_EL1 register has cache attribute information
    for a given cache selection in CSSELR_EL1. However, the
    cache isn't being selected before reading CCSIDR_EL1.
    Instead use CTR_EL0 which better fits with the semantics
    of dcache_line_bytes(). CTR_EL0 has the minimum data cache
    line size of all caches in the system encoded in 19:16 encoded
    as lg(line size in words).
    
    BUG=None
    TEST=Built.
    
    Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/208720
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    (cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0
    Reviewed-on: http://review.coreboot.org/8642
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/8642 for details.

-gerrit