[coreboot-gerrit] Patch set updated for coreboot: 1a30a43 cpu/amd/pi: Enable early decode of the UART on LPC
Dave Frodin (dave.frodin@se-eng.com)
gerrit at coreboot.org
Thu Mar 12 23:40:50 CET 2015
Dave Frodin (dave.frodin at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8661
-gerrit
commit 1a30a438ebdb226db92508c860fb476a3508b9d3
Author: Dave Frodin <dave.frodin at se-eng.com>
Date: Thu Mar 12 16:14:01 2015 -0600
cpu/amd/pi: Enable early decode of the UART on LPC
The decode of UART addresses down to the LPC bus need
to occur early to allow romstage console messages to
be seen.
Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin at se-eng.com>
---
src/cpu/amd/pi/00630F01/fixme.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index f032f02..ccd3b8e 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -67,6 +67,8 @@ void amd_initcpuio(void)
void amd_initmmio(void)
{
UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@@ -83,6 +85,11 @@ void amd_initmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+ /* For serial port */
+ PciData = 0xFF03FFD5;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
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