[coreboot-gerrit] New patch to review for coreboot: 4ff5173 armv8: correct dcache line size calculation

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8642

-gerrit

commit 4ff5173ba97e0dd40851a2ee1f836595285e90f1
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 17 13:08:06 2014 -0500

    armv8: correct dcache line size calculation
    
    The CCSIDR_EL1 register has cache attribute information
    for a given cache selection in CSSELR_EL1. However, the
    cache isn't being selected before reading CCSIDR_EL1.
    Instead use CTR_EL0 which better fits with the semantics
    of dcache_line_bytes(). CTR_EL0 has the minimum data cache
    line size of all caches in the system encoded in 19:16 encoded
    as lg(line size in words).
    
    BUG=None
    TEST=Built.
    
    Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/208720
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    (cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0
---
 src/arch/arm64/armv8/cache.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c
index 97822ff..c1dba92 100644
--- a/src/arch/arm64/armv8/cache.c
+++ b/src/arch/arm64/armv8/cache.c
@@ -46,16 +46,17 @@ void tlb_invalidate_all(void)
 
 unsigned int dcache_line_bytes(void)
 {
-	uint32_t ccsidr;
+	uint32_t ctr_el0;
 	static unsigned int line_bytes = 0;
 
 	if (line_bytes)
 		return line_bytes;
 
-	ccsidr = raw_read_ccsidr_el1();
-	/* [2:0] - Indicates (Log2(number of words in cache line)) - 4 */
-	line_bytes = 1 << ((ccsidr & 0x7) + 4);	/* words per line */
-	line_bytes *= sizeof(uint32_t);	/* bytes per word */
+	ctr_el0 = raw_read_ctr_el0();
+	/* [19:16] - Indicates (Log2(number of words in cache line) */
+	line_bytes = 1 << ((ctr_el0 >> 16) & 0xf);
+	/* Bytes in a word (32-bit) */
+	line_bytes *= sizeof(uint32_t);
 
 	return line_bytes;
 }