[coreboot-gerrit] Patch merged into coreboot/master: 9c8cfc5 coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init
gerrit at coreboot.org
gerrit at coreboot.org
Thu Mar 5 17:32:11 CET 2015
the following patch was just integrated into master:
commit 9c8cfc5c25876991751ff4e533a0c421203139c8
Author: Furquan Shaikh <furquan at google.com>
Date: Mon Jul 14 11:50:09 2014 -0700
coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init
Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and
SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR
registers should be done with proper bitmask.
BUG=None
BRANCH=None
TEST=Compiles successfully and verified that the RES bits are preserved across
register writes.
Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607
Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/207815
Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
(cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9
Reviewed-on: http://review.coreboot.org/8592
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin at google.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/8592 for details.
-gerrit
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