[coreboot-gerrit] Patch set updated for coreboot: a3216d9 rush_ryu: Add new mainboard
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Thu Mar 5 03:59:37 CET 2015
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8594
-gerrit
commit a3216d99626dfaacc8cda7f7e822981f027700a5
Author: Aaron Durbin <adurbin at chromium.org>
Date: Mon Jul 14 19:09:23 2014 -0500
rush_ryu: Add new mainboard
This is a clone of rush for the time being. All the incompatible
bits can be moved later. Additional patches to follow.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built coreboot for rush_ryu board
Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207838
Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
(cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab
---
src/mainboard/google/Kconfig | 3 +
src/mainboard/google/rush_ryu/Kconfig | 70 +++++
src/mainboard/google/rush_ryu/Makefile.inc | 39 +++
src/mainboard/google/rush_ryu/bct/Makefile.inc | 27 ++
src/mainboard/google/rush_ryu/bct/cfg2inc.sh | 34 +++
src/mainboard/google/rush_ryu/bct/emmc.cfg | 13 +
src/mainboard/google/rush_ryu/bct/jtag.cfg | 16 ++
src/mainboard/google/rush_ryu/bct/odmdata.cfg | 1 +
.../google/rush_ryu/bct/sdram-hynix-2GB-792.inc | 311 +++++++++++++++++++++
.../google/rush_ryu/bct/sdram-hynix-2GB-924.inc | 311 +++++++++++++++++++++
.../google/rush_ryu/bct/sdram-hynix-4GB-300.inc | 311 +++++++++++++++++++++
.../google/rush_ryu/bct/sdram-hynix-4GB-792.inc | 311 +++++++++++++++++++++
src/mainboard/google/rush_ryu/bct/sdram-unused.inc | 4 +
src/mainboard/google/rush_ryu/bct/spi.cfg | 31 ++
src/mainboard/google/rush_ryu/boardid.c | 38 +++
src/mainboard/google/rush_ryu/boardid.h | 27 ++
src/mainboard/google/rush_ryu/bootblock.c | 90 ++++++
src/mainboard/google/rush_ryu/devicetree.cb | 22 ++
src/mainboard/google/rush_ryu/mainboard.c | 35 +++
src/mainboard/google/rush_ryu/pmic.c | 112 ++++++++
src/mainboard/google/rush_ryu/pmic.h | 48 ++++
src/mainboard/google/rush_ryu/reset.c | 29 ++
src/mainboard/google/rush_ryu/reset.h | 25 ++
src/mainboard/google/rush_ryu/romstage.c | 29 ++
src/mainboard/google/rush_ryu/sdram_configs.c | 57 ++++
25 files changed, 1994 insertions(+)
diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig
index dd77bf3..210bf46 100644
--- a/src/mainboard/google/Kconfig
+++ b/src/mainboard/google/Kconfig
@@ -49,6 +49,8 @@ config BOARD_GOOGLE_RAMBI
bool "Rambi"
config BOARD_GOOGLE_RUSH
bool "Rush"
+config BOARD_GOOGLE_RUSH_RYU
+ bool "Rush Ryu"
config BOARD_GOOGLE_SAMUS
bool "Samus"
config BOARD_GOOGLE_SLIPPY
@@ -74,6 +76,7 @@ source "src/mainboard/google/peach_pit/Kconfig"
source "src/mainboard/google/peppy/Kconfig"
source "src/mainboard/google/rambi/Kconfig"
source "src/mainboard/google/rush/Kconfig"
+source "src/mainboard/google/rush_ryu/Kconfig"
source "src/mainboard/google/samus/Kconfig"
source "src/mainboard/google/slippy/Kconfig"
source "src/mainboard/google/storm/Kconfig"
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig
new file mode 100644
index 0000000..0d93564
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/Kconfig
@@ -0,0 +1,70 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_GOOGLE_RUSH_RYU
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SOC_NVIDIA_TEGRA132
+ select MAINBOARD_HAS_BOOTBLOCK_INIT
+ select BOARD_ROMSIZE_KB_4096
+
+config MAINBOARD_DIR
+ string
+ default google/rush_ryu
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Rush Ryu"
+
+choice
+ prompt "BCT boot media"
+ default RUSH_RYU_BCT_CFG_SPI
+ help
+ Which boot media to configure the BCT for.
+
+config RUSH_RYU_BCT_CFG_SPI
+ bool "SPI"
+ help
+ Configure the BCT for booting from SPI.
+
+config RUSH_RYU_BCT_CFG_EMMC
+ bool "eMMC"
+ help
+ Configure the BCT for booting from eMMC.
+
+endchoice
+
+config BOOT_MEDIA_SPI_BUS
+ int "SPI bus with boot media ROM"
+ range 1 6
+ depends on RUSH_RYU_BCT_CFG_SPI
+ default 4
+ help
+ Which SPI bus the boot media is connected to.
+
+config BOOT_MEDIA_SPI_CHIP_SELECT
+ int "Chip select for SPI boot media"
+ range 0 3
+ depends on RUSH_RYU_BCT_CFG_SPI
+ default 0
+ help
+ Which chip select to use for boot media.
+
+endif # BOARD_GOOGLE_RUSH_RYU
diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc
new file mode 100644
index 0000000..3c2b5da
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/Makefile.inc
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# Add a handler for BCT config files
+$(call add-special-class,bct-cfg)
+bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2))
+
+$(obj)/generated/bct.cfg:
+ @printf " CAT $(subst $(obj)/,,$(@))\n"
+ cat $^ > $@
+
+subdirs-y += bct
+
+bootblock-y += boardid.c
+bootblock-y += bootblock.c
+bootblock-y += pmic.c
+bootblock-y += reset.c
+
+romstage-y += reset.c
+romstage-y += romstage.c
+romstage-y += sdram_configs.c
+
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/rush_ryu/bct/Makefile.inc b/src/mainboard/google/rush_ryu/bct/Makefile.inc
new file mode 100644
index 0000000..e274fa3
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/Makefile.inc
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_EMMC) += emmc.cfg
+bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_SPI) += spi.cfg
+bct-cfg-y += odmdata.cfg
+bct-cfg-y += jtag.cfg
+
+# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
+# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg".
+# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage.
diff --git a/src/mainboard/google/rush_ryu/bct/cfg2inc.sh b/src/mainboard/google/rush_ryu/bct/cfg2inc.sh
new file mode 100755
index 0000000..a9c629b
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/cfg2inc.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2014 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+bct_cfg2inc() {
+ local in_file="$1"
+ local out_file="$2"
+ echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}"
+ # Note currently we can only handle DDR3 type memory, even in C
+ # implementation.
+ sed "/^#.*$/d; s/^SDRAM.0./ /; s/\r$//; s/;$/,/;" \
+ "${in_file}" >> "${out_file}"
+ echo "}," >>"${out_file}"
+}
+
+for file in $@; do
+ echo "Generating $file => ${file%cfg}inc..."
+ bct_cfg2inc "${file}" "${file%cfg}inc"
+done
diff --git a/src/mainboard/google/rush_ryu/bct/emmc.cfg b/src/mainboard/google/rush_ryu/bct/emmc.cfg
new file mode 100644
index 0000000..430ffd6
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/emmc.cfg
@@ -0,0 +1,13 @@
+# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00130001;
+BlockSize = 0x00004000;
+PageSize = 0x00000200;
+PartitionSize = 0x01000000;
+
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000;
diff --git a/src/mainboard/google/rush_ryu/bct/jtag.cfg b/src/mainboard/google/rush_ryu/bct/jtag.cfg
new file mode 100644
index 0000000..f43e143
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/jtag.cfg
@@ -0,0 +1,16 @@
+#
+# Set JtagCtrl to 1 to reenable Jtag
+#
+JtagCtrl = 0;
+#
+# Fill in chip unique id
+#
+# ChipUid can be found by running tegrarcm in tegra recovery mode
+# (also hooking up A-A USB cable) and looking for console output
+# on line starting with "Chip UID:"
+#
+# Command example:
+# $ sudo tegrarcm --bct=/build/nyan/firmware/bct/board.bct --bootloader=/build/nyan/firmware/u-boot.bin --loadaddr=0x80108000
+# Where board.bct and u-boot.bin do not have to be prebuilt.
+#
+ChipUid = 0x00000000000000000000000000000000;
diff --git a/src/mainboard/google/rush_ryu/bct/odmdata.cfg b/src/mainboard/google/rush_ryu/bct/odmdata.cfg
new file mode 100644
index 0000000..d0ab2bf
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/odmdata.cfg
@@ -0,0 +1 @@
+OdmData = 0x80080000;
diff --git a/src/mainboard/google/rush_ryu/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/rush_ryu/bct/sdram-hynix-2GB-792.inc
new file mode 100644
index 0000000..60bf416
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/sdram-hynix-2GB-792.inc
@@ -0,0 +1,311 @@
+{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */
+ .MemoryType = NvBootMemoryType_Ddr3,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x00000042,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMSelectDiv2 = 0x00000000,
+ .PllMPDLshiftPh45 = 0x00000001,
+ .PllMPDLshiftPh90 = 0x00000001,
+ .PllMPDLshiftPh135 = 0x00000001,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x00000000,
+ .EmcBctSpare5 = 0x00000000,
+ .EmcBctSpare6 = 0x00000000,
+ .EmcBctSpare7 = 0x00000000,
+ .EmcBctSpare8 = 0x00000000,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcClockSource = 0x80000000,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa1430000,
+ .EmcAutoCalConfig2 = 0x00000000,
+ .EmcAutoCalConfig3 = 0x00000000,
+ .EmcAutoCalWait = 0x00000190,
+ .EmcAdrCfg = 0x00000000,
+ .EmcPinProgramWait = 0x00000001,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcTimingControlWait = 0x00000000,
+ .EmcRc = 0x00000025,
+ .EmcRfc = 0x000000cd,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x00000019,
+ .EmcRp = 0x0000000a,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x00000007,
+ .EmcW2r = 0x0000000d,
+ .EmcR2p = 0x00000004,
+ .EmcW2p = 0x00000013,
+ .EmcRdRcd = 0x0000000a,
+ .EmcWrRcd = 0x0000000a,
+ .EmcRrd = 0x00000003,
+ .EmcRext = 0x00000002,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000006,
+ .EmcWdvMask = 0x00000006,
+ .EmcQUse = 0x0000000b,
+ .EmcQuseWidth = 0x00000002,
+ .EmcIbdly = 0x00000000,
+ .EmcEInput = 0x00000003,
+ .EmcEInputDuration = 0x0000000c,
+ .EmcPutermExtra = 0x00090000,
+ .EmcPutermWidth = 0x00000004,
+ .EmcPutermAdj = 0x00000000,
+ .EmcCdbCntl1 = 0x00000000,
+ .EmcCdbCntl2 = 0x00000000,
+ .EmcCdbCntl3 = 0x00000000,
+ .EmcQRst = 0x00000002,
+ .EmcQSafe = 0x00000011,
+ .EmcRdv = 0x00000017,
+ .EmcRdvMask = 0x00000019,
+ .EmcQpop = 0x0000000f,
+ .EmcCtt = 0x00000000,
+ .EmcCttDuration = 0x00000004,
+ .EmcRefresh = 0x000017eb,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x000005fa,
+ .EmcPdEx2Wr = 0x00000003,
+ .EmcPdEx2Rd = 0x00000003,
+ .EmcPChg2Pden = 0x00000001,
+ .EmcAct2Pden = 0x00000000,
+ .EmcAr2Pden = 0x000000c7,
+ .EmcRw2Pden = 0x00000018,
+ .EmcTxsr = 0x000000d7,
+ .EmcTxsrDll = 0x00000200,
+ .EmcTcke = 0x00000005,
+ .EmcTckesr = 0x00000006,
+ .EmcTpd = 0x00000005,
+ .EmcTfaw = 0x0000001d,
+ .EmcTrpab = 0x00000000,
+ .EmcTClkStable = 0x00000008,
+ .EmcTClkStop = 0x00000008,
+ .EmcTRefBw = 0x0000182c,
+ .EmcFbioCfg5 = 0x104ab898,
+ .EmcFbioCfg6 = 0x00000002,
+ .EmcFbioSpare = 0x00000000,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x80001d71,
+ .EmcEmrs = 0x80100002,
+ .EmcEmrs2 = 0x80200018,
+ .EmcEmrs3 = 0x80300000,
+ .EmcMrw1 = 0x00000000,
+ .EmcMrw2 = 0x00000000,
+ .EmcMrw3 = 0x00000000,
+ .EmcMrw4 = 0x00000000,
+ .EmcMrwExtra = 0x00000000,
+ .EmcWarmBootMrwExtra = 0x00000000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x00f7000e,
+ .EmcMrsWaitCnt2 = 0x00f7000e,
+ .EmcCfg = 0x73300000,
+ .EmcCfg2 = 0x0000089d,
+ .EmcCfgPipe = 0x000040a0,
+ .EmcDbg = 0x01000c00,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x80003025,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0xe00701b1,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000002,
+ .EmcSelDpdCtrl = 0x00040000,
+ .EmcDllXformDqs0 = 0x00000008,
+ .EmcDllXformDqs1 = 0x00000008,
+ .EmcDllXformDqs2 = 0x00000008,
+ .EmcDllXformDqs3 = 0x00000008,
+ .EmcDllXformDqs4 = 0x00000008,
+ .EmcDllXformDqs5 = 0x00000008,
+ .EmcDllXformDqs6 = 0x00000008,
+ .EmcDllXformDqs7 = 0x00000008,
+ .EmcDllXformDqs8 = 0x00000008,
+ .EmcDllXformDqs9 = 0x00000008,
+ .EmcDllXformDqs10 = 0x00000008,
+ .EmcDllXformDqs11 = 0x00000008,
+ .EmcDllXformDqs12 = 0x00000008,
+ .EmcDllXformDqs13 = 0x00000008,
+ .EmcDllXformDqs14 = 0x00000008,
+ .EmcDllXformDqs15 = 0x00000008,
+ .EmcDllXformQUse0 = 0x00000000,
+ .EmcDllXformQUse1 = 0x00000000,
+ .EmcDllXformQUse2 = 0x00000000,
+ .EmcDllXformQUse3 = 0x00000000,
+ .EmcDllXformQUse4 = 0x00000000,
+ .EmcDllXformQUse5 = 0x00000000,
+ .EmcDllXformQUse6 = 0x00000000,
+ .EmcDllXformQUse7 = 0x00000000,
+ .EmcDllXformAddr0 = 0x0000000e,
+ .EmcDllXformAddr1 = 0x0000000e,
+ .EmcDllXformAddr2 = 0x00000000,
+ .EmcDllXformAddr3 = 0x0000000e,
+ .EmcDllXformAddr4 = 0x00000000,
+ .EmcDllXformAddr5 = 0x00000000,
+ .EmcDllXformQUse8 = 0x00000000,
+ .EmcDllXformQUse9 = 0x00000000,
+ .EmcDllXformQUse10 = 0x00000000,
+ .EmcDllXformQUse11 = 0x00000000,
+ .EmcDllXformQUse12 = 0x00000000,
+ .EmcDllXformQUse13 = 0x00000000,
+ .EmcDllXformQUse14 = 0x00000000,
+ .EmcDllXformQUse15 = 0x00000000,
+ .EmcDliTrimTxDqs0 = 0x00000000,
+ .EmcDliTrimTxDqs1 = 0x00000000,
+ .EmcDliTrimTxDqs2 = 0x00000000,
+ .EmcDliTrimTxDqs3 = 0x00000000,
+ .EmcDliTrimTxDqs4 = 0x00000000,
+ .EmcDliTrimTxDqs5 = 0x00000000,
+ .EmcDliTrimTxDqs6 = 0x00000000,
+ .EmcDliTrimTxDqs7 = 0x00000000,
+ .EmcDliTrimTxDqs8 = 0x00000000,
+ .EmcDliTrimTxDqs9 = 0x00000000,
+ .EmcDliTrimTxDqs10 = 0x00000000,
+ .EmcDliTrimTxDqs11 = 0x00000000,
+ .EmcDliTrimTxDqs12 = 0x00000000,
+ .EmcDliTrimTxDqs13 = 0x00000000,
+ .EmcDliTrimTxDqs14 = 0x00000000,
+ .EmcDliTrimTxDqs15 = 0x00000000,
+ .EmcDllXformDq0 = 0x0000000b,
+ .EmcDllXformDq1 = 0x0000000b,
+ .EmcDllXformDq2 = 0x0000000b,
+ .EmcDllXformDq3 = 0x0000000b,
+ .EmcDllXformDq4 = 0x0000000b,
+ .EmcDllXformDq5 = 0x0000000b,
+ .EmcDllXformDq6 = 0x0000000b,
+ .EmcDllXformDq7 = 0x0000000b,
+ .WarmBootWait = 0x00000002,
+ .EmcCttTermCtrl = 0x00000802,
+ .EmcOdtWrite = 0x00000000,
+ .EmcOdtRead = 0x00000000,
+ .EmcZcalInterval = 0x00020000,
+ .EmcZcalWaitCnt = 0x00000042,
+ .EmcZcalMrwCmd = 0x80000000,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000011,
+ .EmcZcalInitDev1 = 0x00000000,
+ .EmcZcalInitWait = 0x00000001,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000000,
+ .EmcZcalWarmBootWait = 0x00000001,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x80001d71,
+ .EmcWarmBootMrsExtra = 0x80100002,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .McDisExtraSnapLevels = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000002,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x00000003,
+ .PmcDdrCfg = 0x00002002,
+ .PmcIoDpd3Req = 0x4fff2f97,
+ .PmcIoDpd3ReqWait = 0x00000000,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcPorDpdCtrlWait = 0x00000000,
+ .EmcXm2CmdPadCtrl = 0x100002a0,
+ .EmcXm2CmdPadCtrl2 = 0x770c0000,
+ .EmcXm2CmdPadCtrl3 = 0x050c0000,
+ .EmcXm2CmdPadCtrl4 = 0x00000000,
+ .EmcXm2CmdPadCtrl5 = 0x00111111,
+ .EmcXm2DqsPadCtrl = 0x770c1414,
+ .EmcXm2DqsPadCtrl2 = 0x0020013d,
+ .EmcXm2DqsPadCtrl3 = 0x61861820,
+ .EmcXm2DqsPadCtrl4 = 0x00514514,
+ .EmcXm2DqsPadCtrl5 = 0x00514514,
+ .EmcXm2DqsPadCtrl6 = 0x61861800,
+ .EmcXm2DqPadCtrl = 0x770c2990,
+ .EmcXm2DqPadCtrl2 = 0x00000000,
+ .EmcXm2DqPadCtrl3 = 0x00000000,
+ .EmcXm2ClkPadCtrl = 0x77ffc085,
+ .EmcXm2ClkPadCtrl2 = 0x00000707,
+ .EmcXm2CompPadCtrl = 0x81f1f108,
+ .EmcXm2VttGenPadCtrl = 0x07070004,
+ .EmcXm2VttGenPadCtrl2 = 0x00000000,
+ .EmcXm2VttGenPadCtrl3 = 0x017fffff,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0ByteCfg = 0x00003120,
+ .EmcSwizzleRank0Byte0 = 0x25143067,
+ .EmcSwizzleRank0Byte1 = 0x45367102,
+ .EmcSwizzleRank0Byte2 = 0x47106253,
+ .EmcSwizzleRank0Byte3 = 0x04362175,
+ .EmcSwizzleRank1ByteCfg = 0x00003120,
+ .EmcSwizzleRank1Byte0 = 0x71546032,
+ .EmcSwizzleRank1Byte1 = 0x35104276,
+ .EmcSwizzleRank1Byte2 = 0x27043615,
+ .EmcSwizzleRank1Byte3 = 0x72306145,
+ .EmcDsrVttgenDrv = 0x0505003f,
+ .EmcTxdsrvttgen = 0x00000000,
+ .EmcBgbiasCtl0 = 0x00000000,
+ .McEmemAdrCfg = 0x00000000,
+ .McEmemAdrCfgDev0 = 0x00080303,
+ .McEmemAdrCfgDev1 = 0x00080303,
+ .McEmemAdrCfgBankMask0 = 0x00001248,
+ .McEmemAdrCfgBankMask1 = 0x00002490,
+ .McEmemAdrCfgBankMask2 = 0x00000920,
+ .McEmemAdrCfgBankSwizzle3 = 0x00000001,
+ .McEmemCfg = 0x00000800,
+ .McEmemArbCfg = 0x0e00000b,
+ .McEmemArbOutstandingReq = 0x80000040,
+ .McEmemArbTimingRcd = 0x00000004,
+ .McEmemArbTimingRp = 0x00000005,
+ .McEmemArbTimingRc = 0x00000013,
+ .McEmemArbTimingRas = 0x0000000c,
+ .McEmemArbTimingFaw = 0x0000000f,
+ .McEmemArbTimingRrd = 0x00000002,
+ .McEmemArbTimingRap2Pre = 0x00000003,
+ .McEmemArbTimingWap2Pre = 0x0000000c,
+ .McEmemArbTimingR2R = 0x00000002,
+ .McEmemArbTimingW2W = 0x00000002,
+ .McEmemArbTimingR2W = 0x00000005,
+ .McEmemArbTimingW2R = 0x00000008,
+ .McEmemArbDaTurns = 0x08050202,
+ .McEmemArbDaCovers = 0x00170e13,
+ .McEmemArbMisc0 = 0x736c2414,
+ .McEmemArbMisc1 = 0x70000f02,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McClkenOverride = 0x00000000,
+ .McStatControl = 0x00000000,
+ .McDisplaySnapRing = 0x00000003,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac743,
+ .McVideoProtectVprOverride1 = 0x00000013,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .EmcCaTrainingEnable = 0x00000000,
+ .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
+ .EmcCaTrainingTimingCntl2 = 0x0000001f,
+ .SwizzleRankByteEncode = 0x0000006f,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0xf8000000,
+ .McMtsCarveoutAdrHi = 0x00000000,
+ .McMtsCarveoutSizeMb = 0x00000080,
+ .McMtsCarveoutRegCtrl = 0x00000001,
+},
diff --git a/src/mainboard/google/rush_ryu/bct/sdram-hynix-2GB-924.inc b/src/mainboard/google/rush_ryu/bct/sdram-hynix-2GB-924.inc
new file mode 100644
index 0000000..44d77cb
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/sdram-hynix-2GB-924.inc
@@ -0,0 +1,311 @@
+{ /* generated from sdram-hynix-2GB-924.cfg; do not edit. */
+ .MemoryType = NvBootMemoryType_Ddr3,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x0000004d,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMSelectDiv2 = 0x00000000,
+ .PllMPDLshiftPh45 = 0x00000001,
+ .PllMPDLshiftPh90 = 0x00000001,
+ .PllMPDLshiftPh135 = 0x00000001,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x00000000,
+ .EmcBctSpare5 = 0x00000000,
+ .EmcBctSpare6 = 0x00000000,
+ .EmcBctSpare7 = 0x00000000,
+ .EmcBctSpare8 = 0x00000000,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcClockSource = 0x80000000,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa1430101,
+ .EmcAutoCalConfig2 = 0x00000000,
+ .EmcAutoCalConfig3 = 0x00000000,
+ .EmcAutoCalWait = 0x00000190,
+ .EmcAdrCfg = 0x00000000,
+ .EmcPinProgramWait = 0x00000001,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcTimingControlWait = 0x00000000,
+ .EmcRc = 0x0000002b,
+ .EmcRfc = 0x000000f0,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x0000001e,
+ .EmcRp = 0x0000000b,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x0000000a,
+ .EmcW2r = 0x0000000f,
+ .EmcR2p = 0x00000005,
+ .EmcW2p = 0x00000016,
+ .EmcRdRcd = 0x0000000b,
+ .EmcWrRcd = 0x0000000b,
+ .EmcRrd = 0x00000004,
+ .EmcRext = 0x00000002,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000007,
+ .EmcWdvMask = 0x00000007,
+ .EmcQUse = 0x0000000d,
+ .EmcQuseWidth = 0x00000002,
+ .EmcIbdly = 0x00000000,
+ .EmcEInput = 0x00000002,
+ .EmcEInputDuration = 0x0000000f,
+ .EmcPutermExtra = 0x000a0000,
+ .EmcPutermWidth = 0x00000004,
+ .EmcPutermAdj = 0x00000000,
+ .EmcCdbCntl1 = 0x00000000,
+ .EmcCdbCntl2 = 0x00000000,
+ .EmcCdbCntl3 = 0x00000000,
+ .EmcQRst = 0x00000001,
+ .EmcQSafe = 0x00000016,
+ .EmcRdv = 0x0000001a,
+ .EmcRdvMask = 0x0000001c,
+ .EmcQpop = 0x00000011,
+ .EmcCtt = 0x00000000,
+ .EmcCttDuration = 0x00000004,
+ .EmcRefresh = 0x00001be7,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x000006f9,
+ .EmcPdEx2Wr = 0x00000004,
+ .EmcPdEx2Rd = 0x00000015,
+ .EmcPChg2Pden = 0x00000001,
+ .EmcAct2Pden = 0x00000000,
+ .EmcAr2Pden = 0x000000e7,
+ .EmcRw2Pden = 0x0000001b,
+ .EmcTxsr = 0x000000fb,
+ .EmcTxsrDll = 0x00000200,
+ .EmcTcke = 0x00000006,
+ .EmcTckesr = 0x00000007,
+ .EmcTpd = 0x00000006,
+ .EmcTfaw = 0x00000022,
+ .EmcTrpab = 0x00000000,
+ .EmcTClkStable = 0x0000000a,
+ .EmcTClkStop = 0x0000000a,
+ .EmcTRefBw = 0x00001c28,
+ .EmcFbioCfg5 = 0x104ab898,
+ .EmcFbioCfg6 = 0x00000000,
+ .EmcFbioSpare = 0x00000000,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x80000f15,
+ .EmcEmrs = 0x80100002,
+ .EmcEmrs2 = 0x80200020,
+ .EmcEmrs3 = 0x80300000,
+ .EmcMrw1 = 0x00000000,
+ .EmcMrw2 = 0x00000000,
+ .EmcMrw3 = 0x00000000,
+ .EmcMrw4 = 0x00000000,
+ .EmcMrwExtra = 0x00000000,
+ .EmcWarmBootMrwExtra = 0x00000000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x00cd000e,
+ .EmcMrsWaitCnt2 = 0x00cd000e,
+ .EmcCfg = 0x73300000,
+ .EmcCfg2 = 0x0000089d,
+ .EmcCfgPipe = 0x00004080,
+ .EmcDbg = 0x01000c00,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x800037ea,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0xe00400b1,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000002,
+ .EmcSelDpdCtrl = 0x00040000,
+ .EmcDllXformDqs0 = 0x007fc005,
+ .EmcDllXformDqs1 = 0x007fc005,
+ .EmcDllXformDqs2 = 0x007f8008,
+ .EmcDllXformDqs3 = 0x007f8008,
+ .EmcDllXformDqs4 = 0x007fc005,
+ .EmcDllXformDqs5 = 0x007f8008,
+ .EmcDllXformDqs6 = 0x007fc005,
+ .EmcDllXformDqs7 = 0x007fc005,
+ .EmcDllXformDqs8 = 0x007fc005,
+ .EmcDllXformDqs9 = 0x007fc005,
+ .EmcDllXformDqs10 = 0x007f8008,
+ .EmcDllXformDqs11 = 0x007f8008,
+ .EmcDllXformDqs12 = 0x007fc005,
+ .EmcDllXformDqs13 = 0x007f8008,
+ .EmcDllXformDqs14 = 0x007fc005,
+ .EmcDllXformDqs15 = 0x007fc005,
+ .EmcDllXformQUse0 = 0x00000000,
+ .EmcDllXformQUse1 = 0x00000000,
+ .EmcDllXformQUse2 = 0x00000000,
+ .EmcDllXformQUse3 = 0x00000000,
+ .EmcDllXformQUse4 = 0x00000000,
+ .EmcDllXformQUse5 = 0x00000000,
+ .EmcDllXformQUse6 = 0x00000000,
+ .EmcDllXformQUse7 = 0x00000000,
+ .EmcDllXformAddr0 = 0x00018000,
+ .EmcDllXformAddr1 = 0x00018000,
+ .EmcDllXformAddr2 = 0x00000000,
+ .EmcDllXformAddr3 = 0x00018000,
+ .EmcDllXformAddr4 = 0x00018000,
+ .EmcDllXformAddr5 = 0x00000000,
+ .EmcDllXformQUse8 = 0x00000000,
+ .EmcDllXformQUse9 = 0x00000000,
+ .EmcDllXformQUse10 = 0x00000000,
+ .EmcDllXformQUse11 = 0x00000000,
+ .EmcDllXformQUse12 = 0x00000000,
+ .EmcDllXformQUse13 = 0x00000000,
+ .EmcDllXformQUse14 = 0x00000000,
+ .EmcDllXformQUse15 = 0x00000000,
+ .EmcDliTrimTxDqs0 = 0x00000000,
+ .EmcDliTrimTxDqs1 = 0x00000000,
+ .EmcDliTrimTxDqs2 = 0x00000000,
+ .EmcDliTrimTxDqs3 = 0x00000000,
+ .EmcDliTrimTxDqs4 = 0x00000000,
+ .EmcDliTrimTxDqs5 = 0x00000000,
+ .EmcDliTrimTxDqs6 = 0x00000000,
+ .EmcDliTrimTxDqs7 = 0x00000000,
+ .EmcDliTrimTxDqs8 = 0x00000000,
+ .EmcDliTrimTxDqs9 = 0x00000000,
+ .EmcDliTrimTxDqs10 = 0x00000000,
+ .EmcDliTrimTxDqs11 = 0x00000000,
+ .EmcDliTrimTxDqs12 = 0x00000000,
+ .EmcDliTrimTxDqs13 = 0x00000000,
+ .EmcDliTrimTxDqs14 = 0x00000000,
+ .EmcDliTrimTxDqs15 = 0x00000000,
+ .EmcDllXformDq0 = 0x00000007,
+ .EmcDllXformDq1 = 0x00000007,
+ .EmcDllXformDq2 = 0x00000007,
+ .EmcDllXformDq3 = 0x00000007,
+ .EmcDllXformDq4 = 0x00000007,
+ .EmcDllXformDq5 = 0x00000007,
+ .EmcDllXformDq6 = 0x00000007,
+ .EmcDllXformDq7 = 0x00000007,
+ .WarmBootWait = 0x00000002,
+ .EmcCttTermCtrl = 0x00000802,
+ .EmcOdtWrite = 0x00000000,
+ .EmcOdtRead = 0x00000000,
+ .EmcZcalInterval = 0x00020000,
+ .EmcZcalWaitCnt = 0x0000004c,
+ .EmcZcalMrwCmd = 0x80000000,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000011,
+ .EmcZcalInitDev1 = 0x00000000,
+ .EmcZcalInitWait = 0x00000001,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000000,
+ .EmcZcalWarmBootWait = 0x00000001,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x80000f15,
+ .EmcWarmBootMrsExtra = 0x80100002,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .McDisExtraSnapLevels = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000002,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x00000003,
+ .PmcDdrCfg = 0x00002002,
+ .PmcIoDpd3Req = 0x4fff2f97,
+ .PmcIoDpd3ReqWait = 0x00000000,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcPorDpdCtrlWait = 0x00000000,
+ .EmcXm2CmdPadCtrl = 0x100002a0,
+ .EmcXm2CmdPadCtrl2 = 0x770c0000,
+ .EmcXm2CmdPadCtrl3 = 0x050c0000,
+ .EmcXm2CmdPadCtrl4 = 0x00000000,
+ .EmcXm2CmdPadCtrl5 = 0x00111111,
+ .EmcXm2DqsPadCtrl = 0x770c1414,
+ .EmcXm2DqsPadCtrl2 = 0x0120113d,
+ .EmcXm2DqsPadCtrl3 = 0x5d569720,
+ .EmcXm2DqsPadCtrl4 = 0x00492492,
+ .EmcXm2DqsPadCtrl5 = 0x00552452,
+ .EmcXm2DqsPadCtrl6 = 0x61751800,
+ .EmcXm2DqPadCtrl = 0x770c2990,
+ .EmcXm2DqPadCtrl2 = 0x00000000,
+ .EmcXm2DqPadCtrl3 = 0x00000000,
+ .EmcXm2ClkPadCtrl = 0x77ffc085,
+ .EmcXm2ClkPadCtrl2 = 0x00000000,
+ .EmcXm2CompPadCtrl = 0x81f1f108,
+ .EmcXm2VttGenPadCtrl = 0x07070004,
+ .EmcXm2VttGenPadCtrl2 = 0x00000000,
+ .EmcXm2VttGenPadCtrl3 = 0x016eeeee,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0ByteCfg = 0x00003120,
+ .EmcSwizzleRank0Byte0 = 0x25143067,
+ .EmcSwizzleRank0Byte1 = 0x45367102,
+ .EmcSwizzleRank0Byte2 = 0x47106253,
+ .EmcSwizzleRank0Byte3 = 0x04362175,
+ .EmcSwizzleRank1ByteCfg = 0x00003120,
+ .EmcSwizzleRank1Byte0 = 0x71546032,
+ .EmcSwizzleRank1Byte1 = 0x35104276,
+ .EmcSwizzleRank1Byte2 = 0x27043615,
+ .EmcSwizzleRank1Byte3 = 0x72306145,
+ .EmcDsrVttgenDrv = 0x0606003f,
+ .EmcTxdsrvttgen = 0x00000000,
+ .EmcBgbiasCtl0 = 0x00000000,
+ .McEmemAdrCfg = 0x00000000,
+ .McEmemAdrCfgDev0 = 0x00080303,
+ .McEmemAdrCfgDev1 = 0x00080303,
+ .McEmemAdrCfgBankMask0 = 0x00001248,
+ .McEmemAdrCfgBankMask1 = 0x00002490,
+ .McEmemAdrCfgBankMask2 = 0x00000920,
+ .McEmemAdrCfgBankSwizzle3 = 0x00000001,
+ .McEmemCfg = 0x00000800,
+ .McEmemArbCfg = 0x0e00000d,
+ .McEmemArbOutstandingReq = 0x80000040,
+ .McEmemArbTimingRcd = 0x00000005,
+ .McEmemArbTimingRp = 0x00000006,
+ .McEmemArbTimingRc = 0x00000016,
+ .McEmemArbTimingRas = 0x0000000e,
+ .McEmemArbTimingFaw = 0x00000011,
+ .McEmemArbTimingRrd = 0x00000002,
+ .McEmemArbTimingRap2Pre = 0x00000004,
+ .McEmemArbTimingWap2Pre = 0x0000000e,
+ .McEmemArbTimingR2R = 0x00000002,
+ .McEmemArbTimingW2W = 0x00000002,
+ .McEmemArbTimingR2W = 0x00000007,
+ .McEmemArbTimingW2R = 0x00000009,
+ .McEmemArbDaTurns = 0x09070202,
+ .McEmemArbDaCovers = 0x001a1016,
+ .McEmemArbMisc0 = 0x734e2a17,
+ .McEmemArbMisc1 = 0x70000f02,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McClkenOverride = 0x00000000,
+ .McStatControl = 0x00000000,
+ .McDisplaySnapRing = 0x00000003,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac743,
+ .McVideoProtectVprOverride1 = 0x00000013,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .EmcCaTrainingEnable = 0x00000000,
+ .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
+ .EmcCaTrainingTimingCntl2 = 0x0000001f,
+ .SwizzleRankByteEncode = 0x0000006f,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0xf8000000,
+ .McMtsCarveoutAdrHi = 0x00000000,
+ .McMtsCarveoutSizeMb = 0x00000080,
+ .McMtsCarveoutRegCtrl = 0x00000001,
+},
diff --git a/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-300.inc b/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-300.inc
new file mode 100644
index 0000000..62b067f
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-300.inc
@@ -0,0 +1,311 @@
+{ /* generated from sdram-hynix-4GB-300.cfg, do not edit. */
+ .MemoryType = NvBootMemoryType_Ddr3,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x00000032,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMSelectDiv2 = 0x00000000,
+ .PllMPDLshiftPh45 = 0x00000001,
+ .PllMPDLshiftPh90 = 0x00000001,
+ .PllMPDLshiftPh135 = 0x00000001,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x00000000,
+ .EmcBctSpare5 = 0x00000000,
+ .EmcBctSpare6 = 0x00000000,
+ .EmcBctSpare7 = 0x00000000,
+ .EmcBctSpare8 = 0x00000000,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcClockSource = 0x00000002,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa1430f0f,
+ .EmcAutoCalConfig2 = 0x00000000,
+ .EmcAutoCalConfig3 = 0x00000000,
+ .EmcAutoCalWait = 0x00000190,
+ .EmcAdrCfg = 0x00000001,
+ .EmcPinProgramWait = 0x00000001,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcTimingControlWait = 0x00000000,
+ .EmcRc = 0x0000000d,
+ .EmcRfc = 0x00000067,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x00000009,
+ .EmcRp = 0x00000003,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x00000005,
+ .EmcW2r = 0x00000008,
+ .EmcR2p = 0x00000002,
+ .EmcW2p = 0x00000009,
+ .EmcRdRcd = 0x00000003,
+ .EmcWrRcd = 0x00000003,
+ .EmcRrd = 0x00000002,
+ .EmcRext = 0x00000002,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000003,
+ .EmcWdvMask = 0x00000003,
+ .EmcQUse = 0x00000005,
+ .EmcQuseWidth = 0x00000002,
+ .EmcIbdly = 0x00000000,
+ .EmcEInput = 0x00000002,
+ .EmcEInputDuration = 0x00000007,
+ .EmcPutermExtra = 0x00020000,
+ .EmcPutermWidth = 0x00000003,
+ .EmcPutermAdj = 0x00000000,
+ .EmcCdbCntl1 = 0x00000000,
+ .EmcCdbCntl2 = 0x00000000,
+ .EmcCdbCntl3 = 0x00000000,
+ .EmcQRst = 0x00000001,
+ .EmcQSafe = 0x0000000e,
+ .EmcRdv = 0x00000010,
+ .EmcRdvMask = 0x00000012,
+ .EmcQpop = 0x00000009,
+ .EmcCtt = 0x00000000,
+ .EmcCttDuration = 0x00000003,
+ .EmcRefresh = 0x000008e4,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x00000239,
+ .EmcPdEx2Wr = 0x00000001,
+ .EmcPdEx2Rd = 0x00000008,
+ .EmcPChg2Pden = 0x00000001,
+ .EmcAct2Pden = 0x00000000,
+ .EmcAr2Pden = 0x00000065,
+ .EmcRw2Pden = 0x0000000e,
+ .EmcTxsr = 0x0000006c,
+ .EmcTxsrDll = 0x00000200,
+ .EmcTcke = 0x00000004,
+ .EmcTckesr = 0x00000005,
+ .EmcTpd = 0x00000004,
+ .EmcTfaw = 0x00000009,
+ .EmcTrpab = 0x00000000,
+ .EmcTClkStable = 0x00000005,
+ .EmcTClkStop = 0x00000005,
+ .EmcTRefBw = 0x00000924,
+ .EmcFbioCfg5 = 0x104ab098,
+ .EmcFbioCfg6 = 0x00000000,
+ .EmcFbioSpare = 0x00000000,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x00000321,
+ .EmcEmrs = 0x00100002,
+ .EmcEmrs2 = 0x00200000,
+ .EmcEmrs3 = 0x00300000,
+ .EmcMrw1 = 0x00000000,
+ .EmcMrw2 = 0x00000000,
+ .EmcMrw3 = 0x00000000,
+ .EmcMrw4 = 0x00000000,
+ .EmcMrwExtra = 0x00000000,
+ .EmcWarmBootMrwExtra = 0x00000000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x0117000e,
+ .EmcMrsWaitCnt2 = 0x0117000e,
+ .EmcCfg = 0x73340000,
+ .EmcCfg2 = 0x000008d5,
+ .EmcCfgPipe = 0x000052a3,
+ .EmcDbg = 0x01000c00,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x800012d7,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0x002c00a0,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000000,
+ .EmcSelDpdCtrl = 0x00040128,
+ .EmcDllXformDqs0 = 0x00030000,
+ .EmcDllXformDqs1 = 0x00030000,
+ .EmcDllXformDqs2 = 0x00030000,
+ .EmcDllXformDqs3 = 0x00030000,
+ .EmcDllXformDqs4 = 0x00030000,
+ .EmcDllXformDqs5 = 0x00030000,
+ .EmcDllXformDqs6 = 0x00030000,
+ .EmcDllXformDqs7 = 0x00030000,
+ .EmcDllXformDqs8 = 0x00030000,
+ .EmcDllXformDqs9 = 0x00030000,
+ .EmcDllXformDqs10 = 0x00030000,
+ .EmcDllXformDqs11 = 0x00030000,
+ .EmcDllXformDqs12 = 0x00030000,
+ .EmcDllXformDqs13 = 0x00030000,
+ .EmcDllXformDqs14 = 0x00030000,
+ .EmcDllXformDqs15 = 0x00030000,
+ .EmcDllXformQUse0 = 0x00000000,
+ .EmcDllXformQUse1 = 0x00000000,
+ .EmcDllXformQUse2 = 0x00000000,
+ .EmcDllXformQUse3 = 0x00000000,
+ .EmcDllXformQUse4 = 0x00000000,
+ .EmcDllXformQUse5 = 0x00000000,
+ .EmcDllXformQUse6 = 0x00000000,
+ .EmcDllXformQUse7 = 0x00000000,
+ .EmcDllXformAddr0 = 0x00084000,
+ .EmcDllXformAddr1 = 0x00084000,
+ .EmcDllXformAddr2 = 0x00010000,
+ .EmcDllXformAddr3 = 0x00084000,
+ .EmcDllXformAddr4 = 0x00084000,
+ .EmcDllXformAddr5 = 0x00010000,
+ .EmcDllXformQUse8 = 0x00000000,
+ .EmcDllXformQUse9 = 0x00000000,
+ .EmcDllXformQUse10 = 0x00000000,
+ .EmcDllXformQUse11 = 0x00000000,
+ .EmcDllXformQUse12 = 0x00000000,
+ .EmcDllXformQUse13 = 0x00000000,
+ .EmcDllXformQUse14 = 0x00000000,
+ .EmcDllXformQUse15 = 0x00000000,
+ .EmcDliTrimTxDqs0 = 0x00000000,
+ .EmcDliTrimTxDqs1 = 0x00000000,
+ .EmcDliTrimTxDqs2 = 0x00000000,
+ .EmcDliTrimTxDqs3 = 0x00000000,
+ .EmcDliTrimTxDqs4 = 0x00000000,
+ .EmcDliTrimTxDqs5 = 0x00000000,
+ .EmcDliTrimTxDqs6 = 0x00000000,
+ .EmcDliTrimTxDqs7 = 0x00000000,
+ .EmcDliTrimTxDqs8 = 0x00000000,
+ .EmcDliTrimTxDqs9 = 0x00000000,
+ .EmcDliTrimTxDqs10 = 0x00000000,
+ .EmcDliTrimTxDqs11 = 0x00000000,
+ .EmcDliTrimTxDqs12 = 0x00000000,
+ .EmcDliTrimTxDqs13 = 0x00000000,
+ .EmcDliTrimTxDqs14 = 0x00000000,
+ .EmcDliTrimTxDqs15 = 0x00000000,
+ .EmcDllXformDq0 = 0x00060000,
+ .EmcDllXformDq1 = 0x00060000,
+ .EmcDllXformDq2 = 0x00060000,
+ .EmcDllXformDq3 = 0x00060000,
+ .EmcDllXformDq4 = 0x00006000,
+ .EmcDllXformDq5 = 0x00006000,
+ .EmcDllXformDq6 = 0x00006000,
+ .EmcDllXformDq7 = 0x00006000,
+ .WarmBootWait = 0x00000002,
+ .EmcCttTermCtrl = 0x00000802,
+ .EmcOdtWrite = 0x00000000,
+ .EmcOdtRead = 0x00000000,
+ .EmcZcalInterval = 0x00020000,
+ .EmcZcalWaitCnt = 0x00000042,
+ .EmcZcalMrwCmd = 0x00000000,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000011,
+ .EmcZcalInitDev1 = 0x40000011,
+ .EmcZcalInitWait = 0x00000002,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000000,
+ .EmcZcalWarmBootWait = 0x00000002,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x00000321,
+ .EmcWarmBootMrsExtra = 0x00100002,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .McDisExtraSnapLevels = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000002,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x00000003,
+ .PmcDdrCfg = 0x00002002,
+ .PmcIoDpd3Req = 0x4fffffff,
+ .PmcIoDpd3ReqWait = 0x00000000,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcPorDpdCtrlWait = 0x00000000,
+ .EmcXm2CmdPadCtrl = 0x10000280,
+ .EmcXm2CmdPadCtrl2 = 0x770c0000,
+ .EmcXm2CmdPadCtrl3 = 0x050c0000,
+ .EmcXm2CmdPadCtrl4 = 0x00000000,
+ .EmcXm2CmdPadCtrl5 = 0x00111111,
+ .EmcXm2DqsPadCtrl = 0x770c1414,
+ .EmcXm2DqsPadCtrl2 = 0x01231339,
+ .EmcXm2DqsPadCtrl3 = 0x51451420,
+ .EmcXm2DqsPadCtrl4 = 0x00514514,
+ .EmcXm2DqsPadCtrl5 = 0x00514514,
+ .EmcXm2DqsPadCtrl6 = 0x51451400,
+ .EmcXm2DqPadCtrl = 0x770c2990,
+ .EmcXm2DqPadCtrl2 = 0x00000000,
+ .EmcXm2DqPadCtrl3 = 0x00000000,
+ .EmcXm2ClkPadCtrl = 0x77ffc081,
+ .EmcXm2ClkPadCtrl2 = 0x00000000,
+ .EmcXm2CompPadCtrl = 0x81f1f108,
+ .EmcXm2VttGenPadCtrl = 0x07070004,
+ .EmcXm2VttGenPadCtrl2 = 0x00000000,
+ .EmcXm2VttGenPadCtrl3 = 0x016eeeee,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0ByteCfg = 0x00003120,
+ .EmcSwizzleRank0Byte0 = 0x25143067,
+ .EmcSwizzleRank0Byte1 = 0x45367102,
+ .EmcSwizzleRank0Byte2 = 0x47106253,
+ .EmcSwizzleRank0Byte3 = 0x04362175,
+ .EmcSwizzleRank1ByteCfg = 0x00003120,
+ .EmcSwizzleRank1Byte0 = 0x71546032,
+ .EmcSwizzleRank1Byte1 = 0x35104276,
+ .EmcSwizzleRank1Byte2 = 0x27043615,
+ .EmcSwizzleRank1Byte3 = 0x72306145,
+ .EmcDsrVttgenDrv = 0x0000003f,
+ .EmcTxdsrvttgen = 0x00000096,
+ .EmcBgbiasCtl0 = 0x00000000,
+ .McEmemAdrCfg = 0x00000001,
+ .McEmemAdrCfgDev0 = 0x00080303,
+ .McEmemAdrCfgDev1 = 0x00080303,
+ .McEmemAdrCfgBankMask0 = 0x00001248,
+ .McEmemAdrCfgBankMask1 = 0x00002490,
+ .McEmemAdrCfgBankMask2 = 0x00000920,
+ .McEmemAdrCfgBankSwizzle3 = 0x00000001,
+ .McEmemCfg = 0x00001000,
+ .McEmemArbCfg = 0x08000004,
+ .McEmemArbOutstandingReq = 0x80000040,
+ .McEmemArbTimingRcd = 0x00000001,
+ .McEmemArbTimingRp = 0x00000002,
+ .McEmemArbTimingRc = 0x00000007,
+ .McEmemArbTimingRas = 0x00000004,
+ .McEmemArbTimingFaw = 0x00000005,
+ .McEmemArbTimingRrd = 0x00000001,
+ .McEmemArbTimingRap2Pre = 0x00000002,
+ .McEmemArbTimingWap2Pre = 0x00000007,
+ .McEmemArbTimingR2R = 0x00000002,
+ .McEmemArbTimingW2W = 0x00000002,
+ .McEmemArbTimingR2W = 0x00000004,
+ .McEmemArbTimingW2R = 0x00000006,
+ .McEmemArbDaTurns = 0x06040202,
+ .McEmemArbDaCovers = 0x000b0607,
+ .McEmemArbMisc0 = 0x77450e08,
+ .McEmemArbMisc1 = 0x70000f03,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McClkenOverride = 0x00000000,
+ .McStatControl = 0x00000000,
+ .McDisplaySnapRing = 0x00000003,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac743,
+ .McVideoProtectVprOverride1 = 0x00000013,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .EmcCaTrainingEnable = 0x00000000,
+ .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
+ .EmcCaTrainingTimingCntl2 = 0x0000001f,
+ .SwizzleRankByteEncode = 0x0000006f,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0x78000000,
+ .McMtsCarveoutAdrHi = 0x00000001,
+ .McMtsCarveoutSizeMb = 0x00000080,
+ .McMtsCarveoutRegCtrl = 0x00000001,
+},
diff --git a/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-792.inc
new file mode 100644
index 0000000..7e5f666
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-792.inc
@@ -0,0 +1,311 @@
+{ /* generated from sdram-hynix-4GB-792.cfg, do not edit. */
+ .MemoryType = NvBootMemoryType_Ddr3,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x00000042,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMSelectDiv2 = 0x00000000,
+ .PllMPDLshiftPh45 = 0x00000001,
+ .PllMPDLshiftPh90 = 0x00000001,
+ .PllMPDLshiftPh135 = 0x00000001,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x00000000,
+ .EmcBctSpare5 = 0x00000000,
+ .EmcBctSpare6 = 0x00000000,
+ .EmcBctSpare7 = 0x00000000,
+ .EmcBctSpare8 = 0x00000000,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcClockSource = 0x80000000,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa1430808,
+ .EmcAutoCalConfig2 = 0x00000000,
+ .EmcAutoCalConfig3 = 0x00000000,
+ .EmcAutoCalWait = 0x00000190,
+ .EmcAdrCfg = 0x00000001,
+ .EmcPinProgramWait = 0x00000001,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcTimingControlWait = 0x00000000,
+ .EmcRc = 0x00000024,
+ .EmcRfc = 0x00000114,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x00000019,
+ .EmcRp = 0x0000000a,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x00000008,
+ .EmcW2r = 0x0000000d,
+ .EmcR2p = 0x00000004,
+ .EmcW2p = 0x00000013,
+ .EmcRdRcd = 0x0000000a,
+ .EmcWrRcd = 0x0000000a,
+ .EmcRrd = 0x00000003,
+ .EmcRext = 0x00000002,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000006,
+ .EmcWdvMask = 0x00000006,
+ .EmcQUse = 0x0000000b,
+ .EmcQuseWidth = 0x00000002,
+ .EmcIbdly = 0x00000000,
+ .EmcEInput = 0x00000002,
+ .EmcEInputDuration = 0x0000000d,
+ .EmcPutermExtra = 0x00080000,
+ .EmcPutermWidth = 0x00000004,
+ .EmcPutermAdj = 0x00000000,
+ .EmcCdbCntl1 = 0x00000000,
+ .EmcCdbCntl2 = 0x00000000,
+ .EmcCdbCntl3 = 0x00000000,
+ .EmcQRst = 0x00000001,
+ .EmcQSafe = 0x00000014,
+ .EmcRdv = 0x00000017,
+ .EmcRdvMask = 0x00000019,
+ .EmcQpop = 0x0000000f,
+ .EmcCtt = 0x00000000,
+ .EmcCttDuration = 0x00000004,
+ .EmcRefresh = 0x000017e2,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x000005f8,
+ .EmcPdEx2Wr = 0x00000003,
+ .EmcPdEx2Rd = 0x00000011,
+ .EmcPChg2Pden = 0x00000001,
+ .EmcAct2Pden = 0x00000000,
+ .EmcAr2Pden = 0x0000010d,
+ .EmcRw2Pden = 0x00000018,
+ .EmcTxsr = 0x0000011e,
+ .EmcTxsrDll = 0x00000200,
+ .EmcTcke = 0x00000005,
+ .EmcTckesr = 0x00000006,
+ .EmcTpd = 0x00000005,
+ .EmcTfaw = 0x0000001d,
+ .EmcTrpab = 0x00000000,
+ .EmcTClkStable = 0x00000008,
+ .EmcTClkStop = 0x00000008,
+ .EmcTRefBw = 0x00001822,
+ .EmcFbioCfg5 = 0x104ab098,
+ .EmcFbioCfg6 = 0x00000000,
+ .EmcFbioSpare = 0x00000000,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x00000d71,
+ .EmcEmrs = 0x00100002,
+ .EmcEmrs2 = 0x00200018,
+ .EmcEmrs3 = 0x00300000,
+ .EmcMrw1 = 0x00000000,
+ .EmcMrw2 = 0x00000000,
+ .EmcMrw3 = 0x00000000,
+ .EmcMrw4 = 0x00000000,
+ .EmcMrwExtra = 0x00000000,
+ .EmcWarmBootMrwExtra = 0x00000000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x006f000e,
+ .EmcMrsWaitCnt2 = 0x006f000e,
+ .EmcCfg = 0x73300000,
+ .EmcCfg2 = 0x0000089d,
+ .EmcCfgPipe = 0x000040a0,
+ .EmcDbg = 0x01000c00,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x80003012,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0xe00700b1,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000000,
+ .EmcSelDpdCtrl = 0x00040000,
+ .EmcDllXformDqs0 = 0x00000008,
+ .EmcDllXformDqs1 = 0x00000008,
+ .EmcDllXformDqs2 = 0x00000008,
+ .EmcDllXformDqs3 = 0x00000008,
+ .EmcDllXformDqs4 = 0x00000008,
+ .EmcDllXformDqs5 = 0x00000008,
+ .EmcDllXformDqs6 = 0x00000008,
+ .EmcDllXformDqs7 = 0x00000008,
+ .EmcDllXformDqs8 = 0x00000008,
+ .EmcDllXformDqs9 = 0x00000008,
+ .EmcDllXformDqs10 = 0x00000008,
+ .EmcDllXformDqs11 = 0x00000008,
+ .EmcDllXformDqs12 = 0x00000008,
+ .EmcDllXformDqs13 = 0x00000008,
+ .EmcDllXformDqs14 = 0x00000008,
+ .EmcDllXformDqs15 = 0x00000008,
+ .EmcDllXformQUse0 = 0x00000000,
+ .EmcDllXformQUse1 = 0x00000000,
+ .EmcDllXformQUse2 = 0x00000000,
+ .EmcDllXformQUse3 = 0x00000000,
+ .EmcDllXformQUse4 = 0x00000000,
+ .EmcDllXformQUse5 = 0x00000000,
+ .EmcDllXformQUse6 = 0x00000000,
+ .EmcDllXformQUse7 = 0x00000000,
+ .EmcDllXformAddr0 = 0x00038000,
+ .EmcDllXformAddr1 = 0x00038000,
+ .EmcDllXformAddr2 = 0x00000000,
+ .EmcDllXformAddr3 = 0x00038000,
+ .EmcDllXformAddr4 = 0x00038000,
+ .EmcDllXformAddr5 = 0x00000000,
+ .EmcDllXformQUse8 = 0x00000000,
+ .EmcDllXformQUse9 = 0x00000000,
+ .EmcDllXformQUse10 = 0x00000000,
+ .EmcDllXformQUse11 = 0x00000000,
+ .EmcDllXformQUse12 = 0x00000000,
+ .EmcDllXformQUse13 = 0x00000000,
+ .EmcDllXformQUse14 = 0x00000000,
+ .EmcDllXformQUse15 = 0x00000000,
+ .EmcDliTrimTxDqs0 = 0x00000005,
+ .EmcDliTrimTxDqs1 = 0x00000005,
+ .EmcDliTrimTxDqs2 = 0x00000003,
+ .EmcDliTrimTxDqs3 = 0x00000005,
+ .EmcDliTrimTxDqs4 = 0x00000005,
+ .EmcDliTrimTxDqs5 = 0x00000002,
+ .EmcDliTrimTxDqs6 = 0x00000005,
+ .EmcDliTrimTxDqs7 = 0x00000005,
+ .EmcDliTrimTxDqs8 = 0x00000005,
+ .EmcDliTrimTxDqs9 = 0x00000005,
+ .EmcDliTrimTxDqs10 = 0x00000003,
+ .EmcDliTrimTxDqs11 = 0x00000005,
+ .EmcDliTrimTxDqs12 = 0x00000005,
+ .EmcDliTrimTxDqs13 = 0x00000002,
+ .EmcDliTrimTxDqs14 = 0x00000005,
+ .EmcDliTrimTxDqs15 = 0x00000005,
+ .EmcDllXformDq0 = 0x00000009,
+ .EmcDllXformDq1 = 0x0000000c,
+ .EmcDllXformDq2 = 0x00000008,
+ .EmcDllXformDq3 = 0x0000000a,
+ .EmcDllXformDq4 = 0x0000000a,
+ .EmcDllXformDq5 = 0x00000008,
+ .EmcDllXformDq6 = 0x0000000a,
+ .EmcDllXformDq7 = 0x00000008,
+ .WarmBootWait = 0x00000002,
+ .EmcCttTermCtrl = 0x00000802,
+ .EmcOdtWrite = 0x00000000,
+ .EmcOdtRead = 0x00000000,
+ .EmcZcalInterval = 0x00020000,
+ .EmcZcalWaitCnt = 0x00000042,
+ .EmcZcalMrwCmd = 0x00000000,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000011,
+ .EmcZcalInitDev1 = 0x40000011,
+ .EmcZcalInitWait = 0x00000001,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000000,
+ .EmcZcalWarmBootWait = 0x00000001,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x00000d71,
+ .EmcWarmBootMrsExtra = 0x00100002,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .McDisExtraSnapLevels = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000002,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x00000003,
+ .PmcDdrCfg = 0x00002002,
+ .PmcIoDpd3Req = 0x4fffffff,
+ .PmcIoDpd3ReqWait = 0x00000000,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcPorDpdCtrlWait = 0x00000000,
+ .EmcXm2CmdPadCtrl = 0x100002a0,
+ .EmcXm2CmdPadCtrl2 = 0x770c0000,
+ .EmcXm2CmdPadCtrl3 = 0x050c0000,
+ .EmcXm2CmdPadCtrl4 = 0x00000000,
+ .EmcXm2CmdPadCtrl5 = 0x00111111,
+ .EmcXm2DqsPadCtrl = 0x770c1414,
+ .EmcXm2DqsPadCtrl2 = 0x0120113d,
+ .EmcXm2DqsPadCtrl3 = 0x61861820,
+ .EmcXm2DqsPadCtrl4 = 0x00514514,
+ .EmcXm2DqsPadCtrl5 = 0x00514514,
+ .EmcXm2DqsPadCtrl6 = 0x61861800,
+ .EmcXm2DqPadCtrl = 0x770c2990,
+ .EmcXm2DqPadCtrl2 = 0x00000000,
+ .EmcXm2DqPadCtrl3 = 0x00000000,
+ .EmcXm2ClkPadCtrl = 0x77ffc085,
+ .EmcXm2ClkPadCtrl2 = 0x00000000,
+ .EmcXm2CompPadCtrl = 0x81f1f108,
+ .EmcXm2VttGenPadCtrl = 0x07070004,
+ .EmcXm2VttGenPadCtrl2 = 0x00000000,
+ .EmcXm2VttGenPadCtrl3 = 0x016eeeee,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0ByteCfg = 0x00003120,
+ .EmcSwizzleRank0Byte0 = 0x25143067,
+ .EmcSwizzleRank0Byte1 = 0x45367102,
+ .EmcSwizzleRank0Byte2 = 0x47106253,
+ .EmcSwizzleRank0Byte3 = 0x04362175,
+ .EmcSwizzleRank1ByteCfg = 0x00003120,
+ .EmcSwizzleRank1Byte0 = 0x71546032,
+ .EmcSwizzleRank1Byte1 = 0x35104276,
+ .EmcSwizzleRank1Byte2 = 0x27043615,
+ .EmcSwizzleRank1Byte3 = 0x72306145,
+ .EmcDsrVttgenDrv = 0x0606003f,
+ .EmcTxdsrvttgen = 0x00000000,
+ .EmcBgbiasCtl0 = 0x00000000,
+ .McEmemAdrCfg = 0x00000001,
+ .McEmemAdrCfgDev0 = 0x00080303,
+ .McEmemAdrCfgDev1 = 0x00080303,
+ .McEmemAdrCfgBankMask0 = 0x00001248,
+ .McEmemAdrCfgBankMask1 = 0x00002490,
+ .McEmemAdrCfgBankMask2 = 0x00000920,
+ .McEmemAdrCfgBankSwizzle3 = 0x00000001,
+ .McEmemCfg = 0x00001000,
+ .McEmemArbCfg = 0x0e00000b,
+ .McEmemArbOutstandingReq = 0x80000040,
+ .McEmemArbTimingRcd = 0x00000004,
+ .McEmemArbTimingRp = 0x00000005,
+ .McEmemArbTimingRc = 0x00000013,
+ .McEmemArbTimingRas = 0x0000000c,
+ .McEmemArbTimingFaw = 0x0000000f,
+ .McEmemArbTimingRrd = 0x00000002,
+ .McEmemArbTimingRap2Pre = 0x00000003,
+ .McEmemArbTimingWap2Pre = 0x0000000c,
+ .McEmemArbTimingR2R = 0x00000002,
+ .McEmemArbTimingW2W = 0x00000002,
+ .McEmemArbTimingR2W = 0x00000006,
+ .McEmemArbTimingW2R = 0x00000008,
+ .McEmemArbDaTurns = 0x08060202,
+ .McEmemArbDaCovers = 0x00170e13,
+ .McEmemArbMisc0 = 0x746c2414,
+ .McEmemArbMisc1 = 0x70000f02,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McClkenOverride = 0x00000000,
+ .McStatControl = 0x00000000,
+ .McDisplaySnapRing = 0x00000003,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac743,
+ .McVideoProtectVprOverride1 = 0x00000013,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .EmcCaTrainingEnable = 0x00000000,
+ .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
+ .EmcCaTrainingTimingCntl2 = 0x0000001f,
+ .SwizzleRankByteEncode = 0x0000006f,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0x78000000,
+ .McMtsCarveoutAdrHi = 0x00000001,
+ .McMtsCarveoutSizeMb = 0x00000080,
+ .McMtsCarveoutRegCtrl = 0x00000001,
+},
diff --git a/src/mainboard/google/rush_ryu/bct/sdram-unused.inc b/src/mainboard/google/rush_ryu/bct/sdram-unused.inc
new file mode 100644
index 0000000..bef63dc
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/sdram-unused.inc
@@ -0,0 +1,4 @@
+{ /* dummy. */
+ .MemoryType = NvBootMemoryType_Unused,
+ 0,
+},
diff --git a/src/mainboard/google/rush_ryu/bct/spi.cfg b/src/mainboard/google/rush_ryu/bct/spi.cfg
new file mode 100644
index 0000000..a5ded0b
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/spi.cfg
@@ -0,0 +1,31 @@
+# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00130001;
+BlockSize = 32768;
+PageSize = 2048;
+PartitionSize = 4194304;
+
+DevType[0] = NvBootDevType_Spi;
+DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
+
+DevType[1] = NvBootDevType_Spi;
+DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[1].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0;
+
+DevType[2] = NvBootDevType_Spi;
+DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[2].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0;
+
+DevType[3] = NvBootDevType_Spi;
+DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[3].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0;
diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c
new file mode 100644
index 0000000..76bd4d9
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/boardid.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <soc/nvidia/tegra132/gpio.h>
+
+#include "boardid.h"
+
+uint8_t board_id(void)
+{
+ static int id = -1;
+
+ if (id < 0) {
+ id = gpio_get_in_value(GPIO(Q3)) << 0 |
+ gpio_get_in_value(GPIO(T1)) << 1 |
+ gpio_get_in_value(GPIO(X1)) << 2 |
+ gpio_get_in_value(GPIO(X4)) << 3;
+ printk(BIOS_SPEW, "Board ID: %#x.\n", id);
+ }
+
+ return id;
+}
diff --git a/src/mainboard/google/rush_ryu/boardid.h b/src/mainboard/google/rush_ryu/boardid.h
new file mode 100644
index 0000000..aa2ea5f
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/boardid.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_BOARDID_H__
+#define __MAINBOARD_GOOGLE_RUSH_BOARDID_H__
+
+#include <stdint.h>
+
+uint8_t board_id(void);
+
+#endif /* __MAINBOARD_GOOGLE_RUSH_BOARDID_H__ */
diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c
new file mode 100644
index 0000000..51fe9b3
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bootblock.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra132/clk_rst.h>
+#include <soc/nvidia/tegra132/gpio.h>
+#include <soc/nvidia/tegra132/pinmux.h>
+#include <soc/nvidia/tegra132/spi.h> /* FIXME: move back to soc code? */
+
+#include "pmic.h"
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void set_clock_sources(void)
+{
+ /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
+ writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
+
+ clock_configure_source(mselect, PLLP, 102000);
+
+ /* The PMIC is on I2C5 and can run at 400 KHz. */
+ clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
+
+ /* TODO: We should be able to set this to 50MHz, but that did not seem
+ * reliable. */
+ clock_configure_source(sbc4, PLLP, 33333);
+}
+
+void bootblock_mainboard_init(void)
+{
+ set_clock_sources();
+
+ clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
+ CLK_H_I2C5 | CLK_H_APBDMA,
+ 0, CLK_V_MSELECT, 0, 0);
+
+ // Board ID GPIOs, bits 0-3.
+ gpio_input(GPIO(Q3));
+ gpio_input(GPIO(T1));
+ gpio_input(GPIO(X1));
+ gpio_input(GPIO(X4));
+
+ // I2C5 (PMU) clock.
+ pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
+ PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+ // I2C5 (PMU) data.
+ pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
+ PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
+ i2c_init(4);
+ pmic_init(4);
+
+ /* SPI4 data out (MOSI) */
+ pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
+ PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
+ PINMUX_PULL_UP);
+ /* SPI4 data in (MISO) */
+ pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
+ PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
+ PINMUX_PULL_UP);
+ /* SPI4 clock */
+ pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
+ PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ /* SPI4 chip select 0 */
+ pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
+ PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+
+ tegra_spi_init(4);
+}
diff --git a/src/mainboard/google/rush_ryu/devicetree.cb b/src/mainboard/google/rush_ryu/devicetree.cb
new file mode 100644
index 0000000..73836a4
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/devicetree.cb
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip soc/nvidia/tegra132
+ device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
new file mode 100644
index 0000000..9b8e354
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/coreboot_tables.h>
+
+static void mainboard_init(device_t dev)
+{
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "rush",
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/rush_ryu/pmic.c b/src/mainboard/google/rush_ryu/pmic.c
new file mode 100644
index 0000000..5fc3b17
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/pmic.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "boardid.h"
+#include "pmic.h"
+#include "reset.h"
+
+enum {
+ AS3722_I2C_ADDR = 0x40
+};
+
+struct as3722_init_reg {
+ u8 reg;
+ u8 val;
+ u8 delay;
+};
+
+static struct as3722_init_reg init_list[] = {
+ {AS3722_SDO0, 0x3C, 1},
+ {AS3722_SDO1, 0x32, 0},
+ {AS3722_LDO3, 0x59, 0},
+ {AS3722_SDO2, 0x3C, 0},
+ {AS3722_SDO3, 0x00, 0},
+ {AS3722_SDO4, 0x00, 0},
+ {AS3722_SDO5, 0x50, 0},
+ {AS3722_SDO6, 0x28, 1},
+ {AS3722_LDO0, 0x8A, 0},
+ {AS3722_LDO1, 0x00, 0},
+ {AS3722_LDO2, 0x10, 0},
+ {AS3722_LDO4, 0x00, 0},
+ {AS3722_LDO5, 0x00, 0},
+ {AS3722_LDO6, 0x00, 0},
+ {AS3722_LDO7, 0x00, 0},
+ {AS3722_LDO9, 0x00, 0},
+ {AS3722_LDO10, 0x00, 0},
+ {AS3722_LDO11, 0x00, 1},
+};
+
+static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
+{
+ if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) {
+ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
+ __func__, reg, val);
+ /* Reset the SoC on any PMIC write error */
+ cpu_reset();
+ } else {
+ if (delay)
+ udelay(500);
+ }
+}
+
+static void pmic_slam_defaults(unsigned bus)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(init_list); i++) {
+ struct as3722_init_reg *reg = &init_list[i];
+ pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
+ }
+}
+
+void pmic_init(unsigned bus)
+{
+ /*
+ * Don't need to set up VDD_CORE - already done - by OTP
+ * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+ * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+ */
+
+ /* Restore PMIC POR defaults, in case kernel changed 'em */
+ pmic_slam_defaults(bus);
+
+ /* SDO0: Set VDD_CPU to 1.2V. */
+ pmic_write_reg(bus, 0x00, 0x50, 1);
+
+ /* SDO6: Set VDD_GPU to 1.0V. */
+ pmic_write_reg(bus, 0x06, 0x28, 1);
+
+ /* LDO2: Set +1.2V_GEN_AVDD to 1.2V */
+ pmic_write_reg(bus, 0x12, 0x10, 1);
+
+ /*
+ * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
+ * the value (register 0x20 bit 4)
+ */
+ pmic_write_reg(bus, 0x0c, 0x07, 0);
+ pmic_write_reg(bus, 0x20, 0x10, 1);
+
+ printk(BIOS_DEBUG, "PMIC init done\n");
+}
diff --git a/src/mainboard/google/rush_ryu/pmic.h b/src/mainboard/google/rush_ryu/pmic.h
new file mode 100644
index 0000000..b56c513
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/pmic.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_PMIC_H__
+#define __MAINBOARD_GOOGLE_RUSH_PMIC_H__
+
+enum {
+ AS3722_SDO0 = 0,
+ AS3722_SDO1,
+ AS3722_SDO2,
+ AS3722_SDO3,
+ AS3722_SDO4,
+ AS3722_SDO5,
+ AS3722_SDO6,
+
+ AS3722_LDO0 = 0x10,
+ AS3722_LDO1,
+ AS3722_LDO2,
+ AS3722_LDO3,
+ AS3722_LDO4,
+ AS3722_LDO5,
+ AS3722_LDO6,
+ AS3722_LDO7,
+
+ AS3722_LDO9 = 0x19,
+ AS3722_LDO10,
+ AS3722_LDO11,
+};
+
+void pmic_init(unsigned bus);
+
+#endif /* __MAINBOARD_GOOGLE_RUSH_PMIC_H__ */
diff --git a/src/mainboard/google/rush_ryu/reset.c b/src/mainboard/google/rush_ryu/reset.c
new file mode 100644
index 0000000..3816340
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/reset.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/nvidia/tegra132/gpio.h>
+
+#include "reset.h"
+
+void cpu_reset(void)
+{
+ gpio_output(GPIO(I5), 0);
+ while(1);
+}
diff --git a/src/mainboard/google/rush_ryu/reset.h b/src/mainboard/google/rush_ryu/reset.h
new file mode 100644
index 0000000..be723ce
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/reset.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
+#define __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
+
+void cpu_reset(void);
+
+#endif /* __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__ */
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
new file mode 100644
index 0000000..bb173c0
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/romstage.h>
+
+void mainboard_configure_pmc(void)
+{
+}
+
+void mainboard_enable_vdd_cpu(void)
+{
+ /* VDD_CPU is already enabled in bootblock. */
+}
diff --git a/src/mainboard/google/rush_ryu/sdram_configs.c b/src/mainboard/google/rush_ryu/sdram_configs.c
new file mode 100644
index 0000000..462fec2
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/sdram_configs.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <soc/sdram_configs.h>
+
+static struct sdram_params sdram_configs[] = {
+#include "bct/sdram-hynix-2GB-924.inc" /* ram_code = 0000 */
+#include "bct/sdram-hynix-4GB-792.inc" /* ram_code = 0001 */
+#include "bct/sdram-unused.inc" /* ram_code = 0010 */
+#include "bct/sdram-unused.inc" /* ram_code = 0011 */
+#include "bct/sdram-unused.inc" /* ram_code = 0100 */
+#include "bct/sdram-unused.inc" /* ram_code = 0101 */
+#include "bct/sdram-unused.inc" /* ram_code = 0110 */
+#include "bct/sdram-unused.inc" /* ram_code = 0111 */
+#include "bct/sdram-unused.inc" /* ram_code = 1000 */
+#include "bct/sdram-unused.inc" /* ram_code = 1001 */
+#include "bct/sdram-unused.inc" /* ram_code = 1010 */
+#include "bct/sdram-unused.inc" /* ram_code = 1011 */
+#include "bct/sdram-unused.inc" /* ram_code = 1100 */
+#include "bct/sdram-unused.inc" /* ram_code = 1101 */
+#include "bct/sdram-unused.inc" /* ram_code = 1110 */
+#include "bct/sdram-unused.inc" /* ram_code = 1111 */
+};
+
+const struct sdram_params *get_sdram_config()
+{
+ uint32_t ramcode = sdram_get_ram_code();
+ /*
+ * If we need to apply some special hacks to RAMCODE mapping (ex, by
+ * board_id), do that now.
+ */
+
+ printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
+ if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
+ sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) {
+ die("Invalid RAMCODE.");
+ }
+
+ return &sdram_configs[ramcode];
+}
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