[coreboot-gerrit] Patch set updated for coreboot: 7ae4c3f Add stage information to coreboot banner

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Wed Mar 4 19:42:13 CET 2015


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8578

-gerrit

commit 7ae4c3f43871bad2edf2150a28c19f68d60a83cb
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Wed Mar 4 01:11:18 2015 +0100

    Add stage information to coreboot banner
    
    As a convenience, print the actual stage name when entering a stage.
    Also unify the banner between bootblock / romstage and ramstage. No
    reason for two different occurences.
    
    Instead of this:
    
    coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
    [..]
    coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
    [..]
    coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting...
    
    you will see this:
    
    coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting...
    [..]
    coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting...
    [..]
    coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting...
    
    Roughly based on: https://chromium-review.googlesource.com/199671
    
    Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/lib/romcc_console.c |  2 +-
 src/console/init.c               | 12 +++++++++---
 src/lib/hardwaremain.c           |  5 -----
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c
index a6424dd..1f28097 100644
--- a/src/arch/x86/lib/romcc_console.c
+++ b/src/arch/x86/lib/romcc_console.c
@@ -73,7 +73,7 @@ void console_init(void)
 		COREBOOT_EXTRA_VERSION
 		" "
 		COREBOOT_BUILD
-		" starting...\n";
+		" romstage starting...\n";
 
 	console_hw_init();
 
diff --git a/src/console/init.c b/src/console/init.c
index 3dbf014..e638216 100644
--- a/src/console/init.c
+++ b/src/console/init.c
@@ -47,8 +47,14 @@ void console_init(void)
 
 	console_hw_init();
 
-#if defined(__PRE_RAM__)
-	printk(BIOS_INFO, "\n\ncoreboot-%s%s %s starting...\n",
-		      coreboot_version, coreboot_extra_version, coreboot_build);
+	printk(BIOS_INFO, "\n\ncoreboot-%s%s %s %s starting...\n",
+		      coreboot_version, coreboot_extra_version, coreboot_build,
+#if defined(__BOOT_BLOCK__)
+		      "bootblock"
+#elif defined(__PRE_RAM__)
+		      "romstage"
+#else
+		      "ramstage"
 #endif
+		      );
 }
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index d43ff46..32162eb 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -460,11 +460,6 @@ void main(void)
 
 	post_code(POST_CONSOLE_READY);
 
-	printk(BIOS_NOTICE, "coreboot-%s%s %s booting...\n",
-		      coreboot_version, coreboot_extra_version, coreboot_build);
-
-	post_code(POST_CONSOLE_BOOT_MSG);
-
 	/* Handoff sleep type from romstage. */
 #if CONFIG_HAVE_ACPI_RESUME
 	acpi_is_wakeup();



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