[coreboot-gerrit] Patch set updated for coreboot: 70d56bf t132: Add shared romstage
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Wed Mar 4 02:09:49 CET 2015
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8575
-gerrit
commit 70d56bf6086635054d96530562f43a7e7a2c769b
Author: Aaron Durbin <adurbin at chromium.org>
Date: Fri Jun 27 16:43:59 2014 -0500
t132: Add shared romstage
There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.
BUG=None
BRANCH=None
TEST=Built and booted to same place as before.
Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
---
src/mainboard/google/rush/Makefile.inc | 3 +-
src/mainboard/google/rush/romstage.c | 45 ----------------------
src/mainboard/google/rush/sdram_configs.c | 3 +-
src/mainboard/google/rush/sdram_configs.h | 28 --------------
src/soc/nvidia/tegra132/Makefile.inc | 1 +
.../nvidia/tegra132/include/soc/sdram_configs.h | 28 ++++++++++++++
src/soc/nvidia/tegra132/romstage.c | 45 ++++++++++++++++++++++
7 files changed, 76 insertions(+), 77 deletions(-)
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index 746af11..6f4a774 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -32,8 +32,7 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c
bootblock-y += reset.c
-romstage-y += romstage.c
romstage-y += reset.c
romstage-y += sdram_configs.c
-ramstage-y += mainboard.c
\ No newline at end of file
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
deleted file mode 100644
index 9db5298..0000000
--- a/src/mainboard/google/rush/romstage.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/stages.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <arch/exception.h>
-
-#include "sdram_configs.h"
-#include <soc/nvidia/tegra132/sdram.h>
-
-void main(void)
-{
- void *entry;
-
- console_init();
- exception_init();
-
- printk(BIOS_INFO, "T132: romstage here\n");
-
- sdram_init(get_sdram_config());
-
- printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
-
- while (1);
-
- entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
- stage_exit(entry);
-}
diff --git a/src/mainboard/google/rush/sdram_configs.c b/src/mainboard/google/rush/sdram_configs.c
index 18386ac..ea62499 100644
--- a/src/mainboard/google/rush/sdram_configs.c
+++ b/src/mainboard/google/rush/sdram_configs.c
@@ -18,8 +18,7 @@
*/
#include <console/console.h>
-#include <soc/nvidia/tegra132/sdram.h>
-#include "sdram_configs.h"
+#include <soc/sdram_configs.h>
static struct sdram_params sdram_configs[] = {
#include "bct/sdram-hynix-2GB-924.inc" /* ram_code = 0000 */
diff --git a/src/mainboard/google/rush/sdram_configs.h b/src/mainboard/google/rush/sdram_configs.h
deleted file mode 100644
index e00e9ca..0000000
--- a/src/mainboard/google/rush/sdram_configs.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__
-#define __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__
-
-#include <soc/nvidia/tegra132/sdram_param.h>
-
-/* Loads SDRAM configurations for current system. */
-const struct sdram_params *get_sdram_config(void);
-
-#endif /* __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__ */
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 855ef24..a984674 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -24,6 +24,7 @@ romstage-y += spi.c
romstage-y += i2c.c
romstage-y += dma.c
romstage-y += monotonic_timer.c
+romstage-y += romstage.c
romstage-y += sdram.c
romstage-y += sdram_lp0.c
romstage-y += ../tegra/gpio.c
diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_configs.h b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h
new file mode 100644
index 0000000..300be10
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__
+#define __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__
+
+#include <soc/nvidia/tegra132/sdram.h>
+
+/* Loads SDRAM configurations for current system. */
+const struct sdram_params *get_sdram_config(void);
+
+#endif /* __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
new file mode 100644
index 0000000..a4a0636
--- /dev/null
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/stages.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <arch/exception.h>
+
+#include <soc/sdram_configs.h>
+#include <soc/nvidia/tegra132/sdram.h>
+
+void main(void)
+{
+ void *entry;
+
+ console_init();
+ exception_init();
+
+ printk(BIOS_INFO, "T132: romstage here\n");
+
+ sdram_init(get_sdram_config());
+
+ printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
+
+ while (1);
+
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
+ stage_exit(entry);
+}
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