[coreboot-gerrit] Patch set updated for coreboot: armv8 : coreboot for qemu aarch64 #Work in progress#
Naman Govil (namangov@gmail.com)
gerrit at coreboot.org
Fri Jun 26 18:30:59 CEST 2015
Naman Govil (namangov at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10527
-gerrit
commit 6865167fe28242eb1fc56c6f6a01f784414d3079
Author: Naman Govil <namangov at gmail.com>
Date: Wed Jun 10 16:18:52 2015 -0400
armv8 : coreboot for qemu aarch64 #Work in progress#
This patchset aims to add a new mainboard
(emulation) for arm64. By the
end of this work, we will have coreboot running
on a qemu-system-aarch64.
Change-Id: I5550dcaae9981908e0c3bf6961206a70bebac5d1
Signed-off-by: Naman Govil <namangov at gmail.com>
---
src/arch/arm64/cpu-new.h | 204 ++++++++++++++++++++++
src/arch/arm64/include/armv8/arch/secmon.h | 4 +-
src/mainboard/emulation/qemu-armv8/Kconfig | 56 ++++++
src/mainboard/emulation/qemu-armv8/Kconfig.name | 2 +
src/mainboard/emulation/qemu-armv8/Makefile.inc | 37 ++++
src/mainboard/emulation/qemu-armv8/board_info.txt | 3 +
src/mainboard/emulation/qemu-armv8/cbmem.c | 25 +++
src/mainboard/emulation/qemu-armv8/devicetree.cb | 20 +++
src/mainboard/emulation/qemu-armv8/mainboard.c | 27 +++
src/mainboard/emulation/qemu-armv8/media.c | 95 ++++++++++
src/mainboard/emulation/qemu-armv8/memlayout.ld | 48 +++++
src/mainboard/emulation/qemu-armv8/romstage.c | 29 +++
src/mainboard/emulation/qemu-armv8/timer.c | 27 +++
src/mainboard/emulation/qemu-armv8/uart.c | 60 +++++++
util/crossgcc/buildgcc | 2 +-
15 files changed, 636 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm64/cpu-new.h b/src/arch/arm64/cpu-new.h
new file mode 100644
index 0000000..ae16fa1
--- /dev/null
+++ b/src/arch/arm64/cpu-new.h
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_CPU_H__
+#define __ARCH_CPU_H__
+
+#define asmlinkage
+
+#if !defined(__PRE_RAM__)
+#include <arch/barrier.h>
+#include <arch/mpidr.h>
+#include <device/device.h>
+
+enum {
+ CPU_ID_END = 0x00000000,
+};
+
+struct cpu_device_id {
+ uint32_t midr;
+};
+
+struct cpu_driver {
+ /* This is excessive as init() is the only one called. */
+ struct device_operations *ops;
+ const struct cpu_device_id *id_table;
+};
+
+/* Action to run. */
+struct cpu_action {
+ void (*run)(void *arg);
+ void *arg;
+};
+
+/*
+ * Actions are queued to 'todo'. When picked up 'todo' is cleared. The
+ * 'completed' field is set to the original 'todo' value when the action
+ * is complete.
+ */
+struct cpu_action_queue {
+ struct cpu_action *todo;
+ struct cpu_action *completed;
+};
+
+struct cpu_info {
+ device_t cpu;
+ struct cpu_action_queue action_queue;
+ unsigned int online;
+ /* Current assumption is that id matches smp_processor_id(). */
+ unsigned int id;
+ uint64_t mpidr;
+};
+
+/* Obtain cpu_info for current executing CPU. */
+struct cpu_info *cpu_info(void);
+
+extern struct cpu_info *bsp_cpu_info;
+extern struct cpu_info cpu_infos[CONFIG_MAX_CPUS];
+
+static inline struct cpu_info *cpu_info_for_cpu(unsigned int id)
+{
+ return &cpu_infos[id];
+}
+
+/* Ran only by BSP at initial boot strapping. */
+static inline void cpu_set_bsp(void)
+{
+ bsp_cpu_info = cpu_info();
+}
+
+static inline int cpu_is_bsp(void)
+{
+ return cpu_info() == bsp_cpu_info;
+}
+
+static inline int cpu_online(struct cpu_info *ci)
+{
+ return load_acquire(&ci->online) != 0;
+}
+
+static inline void cpu_mark_online(struct cpu_info *ci)
+{
+ ci->mpidr = read_affinity_mpidr();
+ store_release(&ci->online, 1);
+}
+
+/* Provide number of CPUs online. */
+size_t cpus_online(void);
+
+/* Control routines for starting CPUs. */
+struct cpu_control_ops {
+ /* Return the maximum number of CPUs supported. */
+ size_t (*total_cpus)(void);
+ /*
+ * Start the requested CPU and have it start running entry().
+ * Returns 0 on success, < 0 on error.
+ */
+ int (*start_cpu)(unsigned int id, void (*entry)(void));
+};
+
+/*
+ * Initialize all DEVICE_PATH_CPUS under the DEVICE_PATH_CPU_CLUSTER cluster.
+ * type DEVICE_PATH_CPUS. Start up is controlled by cntrl_ops.
+ */
+void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops);
+
+/*
+ * Run cpu_action returning < 0 on error, 0 on success. There are synchronous
+ * and asynchronous methods. Both cases ensure the action has been picked up
+ * by the target cpu. The synchronous variants will wait for the action to
+ * be completed before returning.
+ *
+ * Though the current implementation allows queuing actions on the main cpu,
+ * the main cpu doesn't process its own queue.
+ */
+int arch_run_on_cpu(unsigned int cpu, struct cpu_action *action);
+int arch_run_on_all_cpus(struct cpu_action *action);
+int arch_run_on_all_cpus_but_self(struct cpu_action *action);
+int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action);
+int arch_run_on_all_cpus_async(struct cpu_action *action);
+int arch_run_on_all_cpus_but_self_async(struct cpu_action *action);
+
+/* Wait for actions to be perfomed. */
+void arch_cpu_wait_for_action(void);
+
+#endif /* !__PRE_RAM__ */
+
+/*
+ * Returns logical cpu in range [0:MAX_CPUS). SoC should define this.
+ * Additionally, this is needed early in arm64 init so it should not
+ * rely on a stack. Standard clobber list is fair game: x0-x7 and x0
+ * returns the logical cpu number.
+ */
+unsigned int smp_processor_id(void);
+
+/*
+ * Stages and rmodules have 2 entry points: BSP and non-BSP. Provided
+ * a pointer the correct non-BSP entry point will be returned. The
+ * first instruction is for BSP and the 2nd is for non-BSP. Instructions
+ * are all 32-bit on arm64.
+ */
+static inline void *secondary_entry_point(void *e)
+{
+ uintptr_t nonbsp = (uintptr_t)e;
+
+ return (void *)(nonbsp + sizeof(uint32_t));
+}
+
+/*
+ * The arm64_cpu_startup() initializes a CPU's exception stack and regular
+ * stack as well initializing the C environment for the processor. It
+ * calls into the array of function pointers at symbol c_entry depending
+ * on BSP state. Note that arm64_cpu_startup contains secondary entry
+ * point which can be obtained by secondary_entry_point().
+ */
+void arm64_cpu_startup(void);
+
+/*
+ * The arm64_cpu_startup_resume() initializes a CPU's exception stack and
+ * regular stack as well initializing the C environment for the processor. It
+ * calls into the array of function pointers at symbol c_entry depending
+ * on BSP state. Note that arm64_cpu_startup contains secondary entry
+ * point which can be obtained by secondary_entry_point().
+ * Additionally, it also restores saved register data and enables MMU, caches
+ * and exceptions before jumping to C environment for both BSP and non-BSP CPUs.
+ */
+void arm64_cpu_startup_resume(void);
+
+/*
+ * The arm64_arch_timer_init() initializes the per CPU's cntfrq register of
+ * ARM arch timer.
+ */
+void arm64_arch_timer_init(void);
+
+/*
+ * The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM.
+ * L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported.
+ */
+#define NO_L2_FLUSH 0
+#define L2_FLUSH_HW 0
+#define L2_FLUSH_SW 1
+
+#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT)
+void cortex_a57_cpu_power_down(int l2_flush);
+#else
+static inline void cortex_a57_cpu_power_down(int l2_flush) {}
+#endif
+
+#endif /* __ARCH_CPU_H__ */
diff --git a/src/arch/arm64/include/armv8/arch/secmon.h b/src/arch/arm64/include/armv8/arch/secmon.h
index f8351b5..6458893 100644
--- a/src/arch/arm64/include/armv8/arch/secmon.h
+++ b/src/arch/arm64/include/armv8/arch/secmon.h
@@ -24,8 +24,8 @@
struct secmon_params {
size_t online_cpus;
- struct cpu_action bsp;
- struct cpu_action secondary;
+ struct cpu_action *bsp;
+ struct cpu_action *secondary;
};
void secmon_run(void (*entry)(void *), void *arg);
diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig b/src/mainboard/emulation/qemu-armv8/Kconfig
new file mode 100644
index 0000000..2f4b94f
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/Kconfig
@@ -0,0 +1,56 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015, Naman Govil <namangov at gmail.com>
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# WRITE THE INSTRUCTIONS TO EXECUTE
+# To execute, do:
+# export QEMU_AUDIO_DRV=none
+# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
+
+if BOARD_EMULATION_QEMU_ARMV8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select DRIVERS_UART_PL011
+ select BOOTBLOCK_CONSOLE
+ select EARLY_CONSOLE
+ select CONSOLE_SERIAL
+ select ARCH_BOOTBLOCK_ARMV8_64
+ select ARCH_VERSTAGE_ARMV8_64
+ select ARCH_ROMSTAGE_ARMV8_64
+ select ARCH_RAMSTAGE_ARMV8_64
+# select ARCH_ARM64_ARMV8_SECMON
+ select BOARD_ROMSIZE_KB_4096
+
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-armv8
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU ARMv8"
+
+config MAX_CPUS
+ int
+ default 1
+
+config MAINBOARD_VENDOR
+ string
+ default "ARM Ltd."
+
+config DRAM_SIZE_MB
+ int
+ default 1024
+
+endif # BOARD_EMULATION_QEMU_ARMV8
diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig.name b/src/mainboard/emulation/qemu-armv8/Kconfig.name
new file mode 100644
index 0000000..bb3a0e4
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_EMULATION_QEMU_ARMV8
+ bool "QEMU armv8"
diff --git a/src/mainboard/emulation/qemu-armv8/Makefile.inc b/src/mainboard/emulation/qemu-armv8/Makefile.inc
new file mode 100644
index 0000000..28b1fa7
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/Makefile.inc
@@ -0,0 +1,37 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015, Naman Govil <namangov at gmail.com>
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+romstage-y += romstage.c
+
+romstage-y += cbmem.c
+ramstage-y += cbmem.c
+
+bootblock-y += media.c
+romstage-y += media.c
+ramstage-y += media.c
+
+bootblock-y += timer.c
+romstage-y += timer.c
+ramstage-y += timer.c
+
+bootblock-y += uart.c
+romstage-y += uart.c
+ramstage-y += uart.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
+
+
diff --git a/src/mainboard/emulation/qemu-armv8/board_info.txt b/src/mainboard/emulation/qemu-armv8/board_info.txt
new file mode 100644
index 0000000..69c5eb6
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/board_info.txt
@@ -0,0 +1,3 @@
+Board name: QEMU armv8
+Category: emulation
+Board URL: http://fabrice.bellard.free.fr/qemu/
diff --git a/src/mainboard/emulation/qemu-armv8/cbmem.c b/src/mainboard/emulation/qemu-armv8/cbmem.c
new file mode 100644
index 0000000..d3a2d6f
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/cbmem.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stddef.h>
+#include <cbmem.h>
+#include <symbols.h>
+
+void *cbmem_top(void)
+{
+ return _dram + (CONFIG_DRAM_SIZE_MB << 20);
+}
diff --git a/src/mainboard/emulation/qemu-armv8/devicetree.cb b/src/mainboard/emulation/qemu-armv8/devicetree.cb
new file mode 100644
index 0000000..9153442
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# TODO fill with Versatile Express board data in QEMU.
+chip cpu/armltd/cortex-a9
+ chip drivers/generic/generic # I2C0 controller
+ device i2c 6 on end # Fake component for testing
+ end
+end
diff --git a/src/mainboard/emulation/qemu-armv8/mainboard.c b/src/mainboard/emulation/qemu-armv8/mainboard.c
new file mode 100644
index 0000000..b73ab9d
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/mainboard.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Naman Govil, <namangov at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Enable qemu/armv8 device...\n");
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/qemu-armv8/media.c b/src/mainboard/emulation/qemu-armv8/media.c
new file mode 100644
index 0000000..e0f2251
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/media.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <boot_device.h>
+#include <cbfs.h>
+#include <string.h>
+#include <symbols.h>
+#include <console/console.h>
+
+/* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */
+static const struct mem_region_device gboot_dev =
+ MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+ return &gboot_dev.rdev;
+}
+
+static int emu_rom_open(struct cbfs_media *media)
+{
+ return 0;
+}
+
+static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count)
+{
+ const struct region_device *boot_dev;
+ void *ptr;
+
+ boot_dev = media->context;
+
+ ptr = rdev_mmap(boot_dev, offset, count);
+
+ if (ptr == NULL)
+ return (void *)-1;
+
+ return ptr;
+}
+
+static void *emu_rom_unmap(struct cbfs_media *media, const void *address)
+{
+ const struct region_device *boot_dev;
+
+ boot_dev = media->context;
+
+ rdev_munmap(boot_dev, (void *)address);
+
+ return NULL;
+}
+
+static size_t emu_rom_read(struct cbfs_media *media, void *dest, size_t offset,
+ size_t count)
+{
+ const struct region_device *boot_dev;
+
+ boot_dev = media->context;
+
+ if (rdev_readat(boot_dev, dest, offset, count) < 0)
+ return 0;
+
+ return count;
+}
+
+static int emu_rom_close(struct cbfs_media *media)
+{
+ return 0;
+}
+
+static int init_emu_rom_cbfs_media(struct cbfs_media *media)
+{
+ boot_device_init();
+
+ media->context = (void *)boot_device_ro();
+ media->open = emu_rom_open;
+ media->close = emu_rom_close;
+ media->map = emu_rom_map;
+ media->unmap = emu_rom_unmap;
+ media->read = emu_rom_read;
+ return 0;
+}
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ return init_emu_rom_cbfs_media(media);
+}
diff --git a/src/mainboard/emulation/qemu-armv8/memlayout.ld b/src/mainboard/emulation/qemu-armv8/memlayout.ld
new file mode 100644
index 0000000..ee8132d
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/memlayout.ld
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C )2015, Naman Govil <namangov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Memory map for qemu armv8:
+ *
+ * 0x0000_0000: jump instruction (required by qemu)
+ * 0x0001_0000: bootblock (entry of kernel / firmware)
+ * 0x0002_0000: romstage, assume up to 128KB in size.
+ * 0x0007_ff00: stack pointer
+ * 0x0010_0000: CBFS header
+ * 0x0011_0000: CBFS data
+ * 0x0100_0000: reserved for ramstage
+ * 0x1000_0000: I/O map address
+ */
+
+SECTIONS
+{
+ /* TODO: does this thing emulate SRAM? */
+
+ BOOTBLOCK(0x10000, 64K)
+ ROMSTAGE(0x20000, 128K)
+ STACK(0x000FC000, 16K)
+
+ DRAM_START(0x01000000)
+ RAMSTAGE(0x01000000, 16M)
+}
diff --git a/src/mainboard/emulation/qemu-armv8/romstage.c b/src/mainboard/emulation/qemu-armv8/romstage.c
new file mode 100644
index 0000000..fc4de3e
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/romstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015, Naman Govil <namangov at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <arch/stages.h>
+
+void main(void)
+{
+ void *entry;
+ console_init();
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
+ stage_exit(entry);
+ //run_ramstage();
+}
diff --git a/src/mainboard/emulation/qemu-armv8/timer.c b/src/mainboard/emulation/qemu-armv8/timer.c
new file mode 100644
index 0000000..b6d048b
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/timer.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015, Naman Govil <namangov at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+void udelay(unsigned int n);
+void udelay(unsigned int n)
+{
+ /* TODO provide delay here. */
+}
+
+int init_timer(void);
+int init_timer(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/emulation/qemu-armv8/uart.c b/src/mainboard/emulation/qemu-armv8/uart.c
new file mode 100644
index 0000000..b7f7cea
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/uart.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Naman Govil, <namangov at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <uart.h>
+
+#define UART0_IO_ADDRESS (0x1C090000)
+
+static void pl011_init_dev(void) {
+ /*Do we need to make the pins 0 and 8 high?
+ * */
+}
+
+static void pl011_uart_tx_byte(unsigned char data) {
+ static volatile uint32_t *uart0_address =
+ (uint32_t *)UART0_IO_ADDRESS;
+
+ *uart0_address = (uint32_t)data;
+}
+
+static void pl011_uart_tx_flush(void) {
+}
+
+#if !defined(__PRE_RAM__)
+static const struct console_driver pl011_uart_console __console = {
+ .init = pl011_init_dev,
+ .tx_byte = pl011_uart_tx_byte,
+ .tx_flush = pl011_uart_tx_flush,
+};
+
+uint32_t uartmem_getbaseaddr(void)
+{
+ return UART0_IO_ADDRESS;
+}
+
+#else
+void uart_init(void){
+ pl011_init_dev();
+}
+
+void uart_tx_byte(unsigned char data){
+ pl011_uart_tx_byte(data);
+}
+
+void uart_tx_flush(void) {
+ pl011_uart_tx_flush();
+}
+#endif
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b78b141..f7a8023 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -387,7 +387,7 @@ build_BINUTILS() {
fi
CC="$CC" ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR \
--target=${TARGETARCH} --enable-targets=${TARGETARCH}${ADDITIONALTARGET} \
- --disable-werror --disable-nls --enable-lto --enable-gold \
+ --disable-werror --disable-nls --enable-lto \
--enable-plugins --enable-multilibs CFLAGS="$HOSTCFLAGS" || touch .failed
$MAKE $JOBS || touch .failed
$MAKE install DESTDIR=$DESTDIR || touch .failed
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