[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/cyan: Cyan board support

Leroy P Leahy (leroy.p.leahy@intel.com) gerrit at coreboot.org
Fri Jun 26 02:27:18 CEST 2015


Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10182

-gerrit

commit 6fd313b7997071323ec12dfbb981129af416d423
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Mon May 11 17:24:31 2015 -0700

    mainboard/google/cyan: Cyan board support
    
    Add initial files for the cyan board.
    
    BRANCH=none
    BUG=None
    Test=Build and run on cyan
    
    Change-Id: I935839be033c25e197e78fbee306104b4162a99a
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/mainboard/google/cyan/Kconfig                  |  72 ++++++
 src/mainboard/google/cyan/Kconfig.name             |   2 +
 src/mainboard/google/cyan/Makefile.inc             |  35 +++
 src/mainboard/google/cyan/acpi/chromeos.asl        |  37 +++
 src/mainboard/google/cyan/acpi/dptf.asl            |  93 +++++++
 src/mainboard/google/cyan/acpi/ec.asl              |  25 ++
 src/mainboard/google/cyan/acpi/mainboard.asl       | 288 +++++++++++++++++++++
 src/mainboard/google/cyan/acpi/superio.asl         |  34 +++
 src/mainboard/google/cyan/acpi_tables.c            |  66 +++++
 src/mainboard/google/cyan/boardid.c                |  35 +++
 src/mainboard/google/cyan/chromeos.c               | 135 ++++++++++
 src/mainboard/google/cyan/cmos.layout              | 140 ++++++++++
 src/mainboard/google/cyan/com_init.c               |  48 ++++
 src/mainboard/google/cyan/devicetree.cb            | 142 ++++++++++
 src/mainboard/google/cyan/dsdt.asl                 |  58 +++++
 src/mainboard/google/cyan/ec.c                     |  59 +++++
 src/mainboard/google/cyan/ec.h                     |  69 +++++
 src/mainboard/google/cyan/fadt.c                   |  51 ++++
 src/mainboard/google/cyan/gpio.c                   | 276 ++++++++++++++++++++
 src/mainboard/google/cyan/gpio.h                   |  24 ++
 src/mainboard/google/cyan/gpio_pre_evt.c           | 271 +++++++++++++++++++
 src/mainboard/google/cyan/irqroute.c               |  23 ++
 src/mainboard/google/cyan/irqroute.h               |  64 +++++
 src/mainboard/google/cyan/mainboard.c              |  44 ++++
 src/mainboard/google/cyan/onboard.h                |  86 ++++++
 src/mainboard/google/cyan/ramstage.c               |  28 ++
 src/mainboard/google/cyan/romstage.c               |  47 ++++
 src/mainboard/google/cyan/smihandler.c             | 166 ++++++++++++
 src/mainboard/google/cyan/spd/Makefile.inc         |  42 +++
 .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex    |  32 +++
 ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex |  32 +++
 .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex  |  32 +++
 src/mainboard/google/cyan/spd/spd.c                | 192 ++++++++++++++
 src/mainboard/google/cyan/w25q64.c                 |  75 ++++++
 34 files changed, 2823 insertions(+)

diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
new file mode 100644
index 0000000..010cdf9
--- /dev/null
+++ b/src/mainboard/google/cyan/Kconfig
@@ -0,0 +1,72 @@
+if BOARD_GOOGLE_CYAN
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ALWAYS_LOAD_OPROM
+	select BOARD_ROMSIZE_KB_8192
+	select CHROMEOS
+	select CHROMEOS_VBNV_CMOS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_MEC
+	select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
+#	select EC_SOFTWARE_SYNC
+	select ENABLE_BUILTIN_COM1
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select LID_SWITCH
+	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
+	select SOC_INTEL_BRASWELL
+	select VBOOT_DYNAMIC_WORK_BUFFER
+	select VIRTUAL_DEV_SWITCH
+
+config DISPLAY_SPD_DATA
+	bool "Display Memory Serial Presence Detect Data"
+	default n
+	help
+	  When enabled displays the memory configuration data.
+
+config DISPLAY_SPD_DATA
+	bool "Display Memory Serial Presence Detect Data"
+	default n
+	help
+	  When enabled displays the memory SPD data.
+
+config DYNAMIC_VNN_SUPPORT
+	bool "Enables support for Dynamic VNN"
+	default n
+
+config MAINBOARD_DIR
+	string
+	default google/cyan
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Cyan"
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config VBOOT_RAMSTAGE_INDEX
+	hex
+	default 0x2
+
+config VBOOT_REFCODE_INDEX
+	hex
+	default 0x3
+
+if !CONFIG_GOP_SUPPORT
+config VGA_BIOS_FILE
+	string
+	default "3rdparty/blobs/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT
+	default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" if !C0_DISP_SUPPORT
+
+config VGA_BIOS_ID
+	string
+	default "8086,22b1" if C0_DISP_SUPPORT
+	default "8086,22b0" if !C0_DISP_SUPPORT
+endif
+
+endif # BOARD_GOOGLE_CYAN
diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name
new file mode 100644
index 0000000..a4562d3
--- /dev/null
+++ b/src/mainboard/google/cyan/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_CYAN
+	bool "Cyan"
diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc
new file mode 100755
index 0000000..03e90df
--- /dev/null
+++ b/src/mainboard/google/cyan/Makefile.inc
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-y += spd
+
+romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
+romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
+
+ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c
+ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c
+ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_pre_evt.c
+ramstage-y += irqroute.c
+ramstage-y += ramstage.c
+ramstage-y += w25q64.c
+ramstage-y += boardid.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl
new file mode 100644
index 0000000..7db294d
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/chromeos.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Fields are in the following order.
+ * - Type: recovery = 1 developer mode = 2 write protect = 3
+ * - Active Level - if -1 not a valid gpio
+ * - GPIO number encoding - if -1 not a valid gpio
+ * - Chipset Name
+ *
+ * Note: We need to encode gpios within the 4 separate banks
+ * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded
+ * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
+ */
+
+Name(OIPG, Package() {
+	/* No physical recovery button */
+	Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
+	Package () { 0x0003, 1, 0x10016, "Braswell" },
+})
diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl
new file mode 100755
index 0000000..67bdbb4
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/dptf.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2105 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 1 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		6200,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
+
+/* Include DPTF */
+#include <soc/intel/braswell/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl
new file mode 100644
index 0000000..5736c27
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/ec.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2105 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/cyan/ec.h>
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl
new file mode 100755
index 0000000..718494e
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/mainboard.asl
@@ -0,0 +1,288 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <mainboard/google/cyan/onboard.h>
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+		Method (_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+			Return (\LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+		Name (_UID, 1)
+	}
+}
+
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
+Scope (\_SB.I2C1)
+{
+	Device (ETSA)
+	{
+		Name (_HID, "ELAN0001")
+		Name (_DDN, "Elan Touchscreen ")
+		Name (_UID, 5)
+		Name (ISTP, 0) /* TouchScreen */
+
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(BUF0,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					0x10,                     /* SlaveAddress */
+					ControllerInitiated,      /* SlaveMode */
+					400000,                   /* ConnectionSpeed */
+					AddressingMode7Bit,       /* AddressingMode */
+					"\\_SB.I2C1",             /* ResourceSource */
+				)
+				GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+					 "\\_SB.GPSW") { CYAN_TOUCH_GPIO_INDEX }
+
+			} )
+			Name(BUF1,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					0x10,                     /* SlaveAddress */
+					ControllerInitiated,      /* SlaveMode */
+					400000,                   /* ConnectionSpeed */
+					AddressingMode7Bit,       /* AddressingMode */
+					"\\_SB.I2C1",             /* ResourceSource */
+				)
+				GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+					 "\\_SB.GPNC") { CYAN_EVT_TOUCH_GPIO_INDEX }
+
+			} )
+			If (LEqual (\BDID, BOARD_EVT)) {
+				Return (BUF1)
+			} Else {
+				Return (BUF0)
+			}
+		}
+
+		Method (_STA)
+		{
+			If (LEqual (\S1EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
+
+Scope (\_SB.I2C2)
+{
+	/* Maxim Audio Codec */
+	Device (MAXM)   /* Audio Codec driver I2C */
+	{
+		Name (_ADR, 0)
+		Name (_HID, AUDIO_CODEC_HID)
+		Name (_CID, AUDIO_CODEC_CID)
+		Name (_DDN, AUDIO_CODEC_DDN)
+		Name (_UID, 1)
+
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(SBUF,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					AUDIO_CODEC_I2C_ADDR,	/* SlaveAddress: bus address */
+					ControllerInitiated,	/* SlaveMode: default to ControllerInitiated */
+					400000,			/* ConnectionSpeed: in Hz */
+					AddressingMode7Bit,	/* Addressing Mode: default to 7 bit */
+					"\\_SB.I2C2",		/* ResourceSource: I2C bus controller name */
+				)
+
+				GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+					"\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX }
+			} )
+			Return (SBUF)
+		}
+
+		Method (_STA)
+		{
+			If (LEqual (\S2EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+	}
+	Device (TISW)   /* TI Switch driver I2C */
+	{
+		Name (_ADR, 0)
+		Name (_HID, TI_SWITCH_HID)
+		Name (_CID, TI_SWITCH_CID)
+		Name (_DDN, TI_SWITCH_DDN)
+		Name (_UID, 1)
+
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(SBUF,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					TI_SWITCH_I2C_ADDR,	/* SlaveAddress: bus address */
+					ControllerInitiated,	/* SlaveMode: default to ControllerInitiated */
+					400000,	/* ConnectionSpeed: in Hz */
+					AddressingMode7Bit,	/* Addressing Mode: default to 7 bit */
+					"\\_SB.I2C2",	/* ResourceSource: I2C bus controller name */
+				)
+
+				GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+					"\\_SB.GPSW") { CYAN_JACK_TI_GPIO_INDEX }
+
+			} )
+			Return (SBUF)
+		}
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
+
+Scope (\_SB.I2C5)
+{
+	Device (ALSI)
+	{
+		/*
+		 * TODO(dlaurie): Need official HID.
+		 *
+		 * The current HID is created from the Intersil PNP
+		 * Vendor ID "LSD" and a shortened device identifier.
+		 */
+		Name (_HID, EisaId ("LSD2918"))
+		Name (_DDN, "Intersil 29018 Ambient Light Sensor")
+		Name (_UID, 1)
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				0x44,                     /* SlaveAddress */
+				ControllerInitiated,      /* SlaveMode */
+				400000,                   /* ConnectionSpeed */
+				AddressingMode7Bit,       /* AddressingMode */
+				"\\_SB.I2C5",             /* ResourceSource */
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_ALS_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S5EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+	}
+}
+
+Scope (\_SB.I2C6)
+{
+	Device (ETPA)
+	{
+		Name (_HID, "ELAN0000")
+		Name (_DDN, "Elan Touchpad")
+		Name (_UID, 3)
+		Name (ISTP, 1) /* Touchpad */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				0x15,                     /* SlaveAddress */
+				ControllerInitiated,      /* SlaveMode */
+				400000,                   /* ConnectionSpeed */
+				AddressingMode7Bit,       /* AddressingMode */
+				"\\_SB.I2C6",             /* ResourceSource */
+			)
+			GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+				 "\\_SB.GPNC") { CYAN_TRACKPAD_GPIO_INDEX }
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S6EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
+
+Scope (\_SB.LPEA)
+{
+	Name (GBUF, ResourceTemplate ()
+	{
+		/* Jack Detect (index 0) */
+		GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+			"\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX }
+	})
+}
+
+Scope (\_SB.GPNC)
+{
+	Method (_AEI, 0, NotSerialized)  // _AEI: ACPI Event Interrupts
+	{
+		Name (RBUF, ResourceTemplate ()
+		{
+			GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+				"\\_SB.GPNC") { CYAN_SCI_GPIO_INDEX }
+		})
+		Return (RBUF)
+	}
+
+	Method (_E0F, 0, NotSerialized)  // _Exx: Edge-Triggered GPE
+	{
+	}
+}
diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl
new file mode 100755
index 0000000..018fdb0
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/superio.asl
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/cyan/ec.h>
+#include <mainboard/google/cyan/onboard.h>
+
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+/* Override default IRQ settings */
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\
+                                                     BOARD_I8042_IRQ}
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c
new file mode 100755
index 0000000..a88abed
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi_tables.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/acpi.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <string.h>
+#include <types.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+
+	/* Enable USB ports in S3 */
+	gnvs->s3u0 = 1;
+	gnvs->s3u1 = 1;
+
+	/* Disable USB ports in S5 */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* Enable DPTF */
+	gnvs->dpte = 1;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	current = acpi_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/src/mainboard/google/cyan/boardid.c b/src/mainboard/google/cyan/boardid.c
new file mode 100644
index 0000000..9b0aa73
--- /dev/null
+++ b/src/mainboard/google/cyan/boardid.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright(C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <stdlib.h>
+#include "ec/google/chromeec/ec.h"
+
+uint8_t board_id(void)
+{
+	static int id = -1;
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	if (id < 0)
+		id = google_chromeec_get_board_version();
+#endif
+	return id;
+}
+
diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c
new file mode 100644
index 0000000..ed869ba
--- /dev/null
+++ b/src/mainboard/google/cyan/chromeos.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#include "ec.h"
+#include <ec/google/chromeec/ec.h>
+#endif
+#include <soc/gpio.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The WP status pin lives on MF_ISH_GPIO_4 */
+#define WP_STATUS_PAD_CFG0	0x4838
+#define WP_STATUS_PAD_CFG1	0x483C
+
+#if ENV_RAMSTAGE
+#include <boot/coreboot_tables.h>
+
+#define GPIO_COUNT	6
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+
+static int get_lid_switch(void)
+{
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	u8 ec_switches;
+
+	mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1,
+		     &ec_switches, NULL);
+	return !!(ec_switches & EC_SWITCH_LID_OPEN);
+#else
+	/* Default to force open. */
+	return 1;
+#endif
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio *gpio;
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	gpio = gpios->gpios;
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect",
+		     get_write_protect_state());
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
+		     recovery_mode_enabled());
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
+		     get_developer_mode_switch());
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch());
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
+}
+#endif /* ENV_RAMSTAGE */
+
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	u8 ec_switches;
+	u32 ec_events;
+
+	mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1,
+		     &ec_switches, NULL);
+
+	/* If a switch is set, we don't need to look at events. */
+	if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
+		return 1;
+
+	/* Else check if the EC has posted the keyboard recovery event. */
+	ec_events = google_chromeec_get_events_b();
+
+	return !!(ec_events &
+		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+#else
+	return 0;
+#endif
+}
+
+int clear_recovery_mode_switch(void)
+{
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	const uint32_t kb_rec_mask =
+		EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+	/* Unconditionally clear the EC recovery request. */
+	return google_chromeec_clear_events_b(kb_rec_mask);
+#else
+	return 0;
+#endif
+}
+
+int get_write_protect_state(void)
+{
+	/*
+	 * The vboot loader queries this function in romstage. The GPIOs have
+	 * not been set up yet as that configuration is done in ramstage.
+	 * Configuring this GPIO as input so that there isn't any ambiguity
+	 * in the reading.
+	 */
+#if ENV_ROMSTAGE
+	write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0),
+	(PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));
+	write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1),
+		PAD_CONFIG1_DEFAULT0);
+#endif
+
+	/* WP is enabled when the pin is reading high. */
+	return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0))
+		& PAD_VAL_HIGH);
+}
diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout
new file mode 100644
index 0000000..18bf4ce
--- /dev/null
+++ b/src/mainboard/google/cyan/cmos.layout
@@ -0,0 +1,140 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2015 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c
new file mode 100644
index 0000000..b07b205
--- /dev/null
+++ b/src/mainboard/google/cyan/com_init.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/gpio.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+
+void mainboard_pre_console_init(struct romstage_params *params)
+{
+	uint32_t reg;
+	uint32_t *pad_config_reg;
+
+	/* Enable the UART hardware for COM1. */
+	reg = 1;
+	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
+
+	/*
+	 * Set up the pads to select the UART function for Cyan
+	 * AD12 SW16(UART1_DATAIN/UART0_DATAIN)   - Set Mode 2 for UART0_RXD
+	 * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD
+	 */
+	pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD);
+	write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,
+		M2));
+
+	pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD);
+	write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,
+		M2));
+}
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
new file mode 100755
index 0000000..8ad0910
--- /dev/null
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -0,0 +1,142 @@
+chip soc/intel/braswell
+
+	############################################################
+	# Set the parameters for MemoryInit
+	############################################################
+
+	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
+
+	register "PcdMrcInitMmioSize" = "0x0800"
+	register "PcdMrcInitSpdAddr1" = "0xa0"
+	register "PcdMrcInitSpdAddr2" = "0xa2"
+	register "PcdIgdDvmt50PreAlloc" = "1"
+	register "PcdApertureSize" = "2"
+	register "PcdGttSize" = "1"
+
+	############################################################
+	# Set the parameters for SiliconInit
+	############################################################
+
+	register "PcdSdcardMode" = "PCH_ACPI_MODE"
+	register "PcdEnableHsuart0" = "0"
+	register "PcdEnableHsuart1" = "1"
+	register "PcdEnableAzalia" = "1"
+	register "PcdEnableSata" = "1"
+	register "PcdEnableXhci" = "1"
+	register "PcdEnableLpe" = "1"
+	register "PcdEnableDma0" = "1"
+	register "PcdEnableDma1" = "1"
+	register "PcdEnableI2C0" = "1"
+	register "PcdEnableI2C1" = "1"
+	register "PcdEnableI2C2" = "1"
+	register "PcdEnableI2C3" = "1"
+	register "PcdEnableI2C4" = "1"
+	register "PcdEnableI2C5" = "1"
+	register "PcdEnableI2C6" = "1"
+	register "PunitPwrConfigDisable" = "0"	# Enable SVID
+	register "ChvSvidConfig" = "SVID_CONFIG1"
+	register "PcdEmmcMode" = "PCH_ACPI_MODE"
+	register "PcdUsb3ClkSsc" = "1"
+	register "PcdDispClkSsc" = "1"
+	register "PcdSataClkSsc" = "1"
+	register "PcdEnableSata" = "0"		# Disable SATA
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "5"
+	register "Usb2Port0IUsbTxEmphasisEn" = "2"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "3"
+	register "Usb2Port1IUsbTxEmphasisEn" = "2"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "3"
+	register "Usb2Port2IUsbTxEmphasisEn" = "2"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "3"
+	register "Usb2Port3IUsbTxEmphasisEn" = "2"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "3"
+	register "Usb2Port4IUsbTxEmphasisEn" = "2"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
+	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
+	register "PcdSataInterfaceSpeed" = "3"
+	register "PcdPchSsicEnable" = "1"
+	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
+	register "PMIC_I2CBus" = "0"
+	register "ISPEnable" = "0"		# Disable IUNIT
+	register "ISPPciDevConfig" = "3"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# Enable devices in ACPI mode
+	register "lpss_acpi_mode" = "1"
+	register "emmc_acpi_mode" = "1"
+	register "sd_acpi_mode" = "1"
+	register "lpe_acpi_mode" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+					# EDS Table 24-4, Figure 24-5
+		device pci 00.0 on end	# 8086 2280 - SoC transaction router
+		device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
+		device pci 03.0 on end	# 8086 22b8 - Camera and Image Processor
+		device pci 0b.0 on end	# 8086 22dc - ?
+		device pci 10.0 on end	# 8086 2294 - MMC Port
+		device pci 11.0 off end	# 8086 0F15 - SDIO Port
+		device pci 12.0 on end	# 8086 0F16 - SD Port
+		device pci 13.0 off end	# 8086 22a3 - Sata controller
+		device pci 14.0 on end	# 8086 22b5 - USB XHCI - Only 1 USB controller at a time
+		device pci 15.0 on end	# 8086 22a8 - LP Engine Audio
+		device pci 16.0 off end	# 8086 22b7 - USB device
+		device pci 18.0 on end	# 8086 22c0 - SIO - DMA
+		device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
+		device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
+		device pci 18.3 on end	# 8086 22c3 -   I2C Port 3
+		device pci 18.4 on end	# 8086 22c4 -   I2C Port 4
+		device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
+		device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
+		device pci 18.7 on end	# 8086 22c7 -   I2C Port 7
+		device pci 1a.0 on end	# 8086 0F18 - Trusted Execution Engine
+		device pci 1b.0 on end	# 8086 0F04 - HD Audio
+		device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
+		device pci 1c.1 on end	# 8086 0000 - PCIe Root Port 2
+		device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
+		device pci 1c.3 on end	# 8086 0000 - PCIe Root Port 4
+		device pci 1e.0 on end	# 8086 2286 - SIO - DMA
+		device pci 1e.1 off end	# 8086 0F08 -   PWM 1
+		device pci 1e.2 off end	# 8086 0F09 -   PWM 2
+		device pci 1e.3 on end	# 8086 228a -   HSUART 1
+		device pci 1e.4 on end	# 8086 228c -   HSUART 2
+		device pci 1e.5 on end	# 8086 228e -   SPI 1
+		device pci 1e.6 on end	# 8086 2290 -   SPI 2
+		device pci 1e.7 on end	# 8086 22ac -   SPI 3
+		device pci 1f.0 on	# 8086 229c - LPC bridge
+			chip drivers/pc80/tpm
+				# Rising edge interrupt
+				register "irq_polarity" = "2"
+				device pnp 0c31.0 on
+					irq 0x70 = 10
+				end
+			end
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end	# 8086 0F12 - SMBus 0
+	end
+end
diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl
new file mode 100755
index 0000000..9f1db24
--- /dev/null
+++ b/src/mainboard/google/cyan/dsdt.asl
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		/* DSDT revision: ACPI v5.0 */
+	"COREv4",	/* OEM id */
+	"COREBOOT",	/* OEM table id */
+	0x20110725	/* OEM revision */
+)
+{
+	/* Some generic macros */
+	#include <soc/intel/braswell/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/braswell/acpi/globalnvs.asl>
+
+	#include <soc/intel/braswell/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			/* #include <soc/intel/braswell/acpi/northcluster.asl> */
+			#include <soc/intel/braswell/acpi/southcluster.asl>
+                        #include <soc/intel/braswell/acpi/dptf/cpu.asl>
+		}
+
+		/* Dynamic Platform Thermal Framework */
+		#include "acpi/dptf.asl"
+	}
+
+	#include "acpi/chromeos.asl"
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <soc/intel/braswell/acpi/sleepstates.asl>
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c
new file mode 100755
index 0000000..2ed2f52
--- /dev/null
+++ b/src/mainboard/google/cyan/ec.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+
+void mainboard_ec_init(void)
+{
+	printk(BIOS_DEBUG, "mainboard_ec_init\n");
+	post_code(0xf0);
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	/* Restore SCI event mask on resume. */
+	if (acpi_slp_type == 3) {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S3_WAKE_EVENTS);
+
+		/* Disable SMI and wake events */
+		google_chromeec_set_smi_mask(0);
+
+		/* Clear pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+		/*
+		 * Set SCI mask.OS may not generate SMI event to set
+		 * this on S3 resume.
+		 */
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+	} else {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S5_WAKE_EVENTS);
+	}
+
+	/* Clear wake event mask */
+	google_chromeec_set_wake_mask(0);
+#endif
+	post_code(0xf1);
+}
diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h
new file mode 100755
index 0000000..7e70d48
--- /dev/null
+++ b/src/mainboard/google/cyan/ec.h
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+/* GPIO_S0_000 is EC_SCI#, but it is bit 16 in GPE_STS */
+#define EC_SCI_GPI   16
+/* GPIO_S5_07 is EC_SMI#, but it is bit 19 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI   19
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif
diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c
new file mode 100644
index 0000000..45a680a
--- /dev/null
+++ b/src/mainboard/google/cyan/fadt.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/acpi.h>
+#include <string.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	acpi_fill_in_fadt(fadt);
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c
new file mode 100644
index 0000000..537dfe9
--- /dev/null
+++ b/src/mainboard/google/cyan/gpio.c
@@ -0,0 +1,276 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright(C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "irqroute.h"
+#include <soc/gpio.h>
+#include <stdlib.h>
+#include "gpio.h"
+
+/* South East Community */
+static const struct soc_gpio_map gpse_gpio_map[] = {
+	Native_M1,/* MF_PLT_CLK0 */
+	GPIO_NC, /* 01 PWM1 */
+	GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
+	GPIO_NC, /* 03 MF_PLT_CLK4 */
+	GPIO_NC, /* 04 MF_PLT_CLK3 */
+	GPIO_NC, /* PWM0 05 */
+	GPIO_NC, /* 06 MF_PLT_CLK5 */
+	GPIO_NC, /* 07 MF_PLT_CLK2 */
+	GPIO_NC, /* 15 SDMMC2_D3_CD_B */
+	Native_M1, /* 16 SDMMC1_CLK */
+	NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
+	GPIO_NC, /* 18 SDMMC2_D1 */
+	GPIO_NC, /* 19 SDMMC2_CLK */
+	NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
+	GPIO_NC, /* 21 SDMMC2_D2 */
+	GPIO_NC, /* 22 SDMMC2_CMD  */
+	NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
+	NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
+	GPIO_NC, /* 25 SDMMC2_D0 */
+	NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
+	NATIVE_PU20K(1), /* 30 SDMMC3_D1 */
+	Native_M1, /* 31 SDMMC3_CLK */
+	NATIVE_PU20K(1), /* 32 SDMMC3_D3 */
+	NATIVE_PU20K(1), /* 33 SDMMC3_D2 */
+	NATIVE_PU20K(1), /* 34 SDMMC3_CMD */
+	NATIVE_PU20K(1), /* 35 SDMMC3_D0 */
+	NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
+	Native_M1, /* 46 LPC_CLKRUNB */
+	NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
+	Native_M1, /* 48 LPC_FRAMEB */
+	Native_M1, /* 49 MF_LPC_CLKOUT1 */
+	NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
+	Native_M1, /* 51 MF_LPC_CLKOUT0 */
+	NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
+	Native_M1,/* SPI1_MISO */
+	Native_M1, /* 61 SPI1_CS0_B */
+	Native_M1, /* SPI1_CLK */
+	NATIVE_PU20K(1), /* 63 MMC1_D6 */
+	Native_M1, /* 62 SPI1_MOSI */
+	NATIVE_PU20K(1), /* 65 MMC1_D5 */
+	GPIO_NC, /* SPI1_CS1_B  66 */
+	NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
+	NATIVE_PU20K(1), /* 68 MMC1_D7 */
+	GPIO_NC, /* 69 MMC1_RCLK */
+	Native_M1, /* 75  GPO USB_OC1_B */
+	Native_M1, /* 76  PMU_RESETBUTTON_B */
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	/* GPIO_ALERT 77   */
+	Native_M1, /* 78  SDMMC3_PWR_EN_B */
+	GPIO_NC, /* 79  GPI ILB_SERIRQ */
+	Native_M1, /* 80  USB_OC0_B */
+	NATIVE_INT(1, L1), /* 81  SDMMC3_CD_B */
+	GPIO_NC,  /* 82  spkr	 asummed gpio number */
+	Native_M1, /* 83 SUSPWRDNACK */
+	SPARE_PIN,/* 84 spare pin */
+	Native_M1, /* 85 SDMMC3_1P8_EN */
+	GPIO_END
+};
+
+
+/* South West Community */
+static const struct soc_gpio_map  gpsw_gpio_map[] = {
+	GPIO_NC, /* 00 FST_SPI_D2 */
+	Native_M1, /* 01 FST_SPI_D0 */
+	Native_M1, /* 02 FST_SPI_CLK */
+	GPIO_NC, /* 03 FST_SPI_D3 */
+	GPIO_NC, /* GPO FST_SPI_CS1_B */
+	Native_M1, /* 05 FST_SPI_D1 */
+	Native_M1, /* 06 FST_SPI_CS0_B */
+	GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */
+	GPIO_NC, /* 15 UART1_RTS_B */
+	Native_M2, /* 16 UART1_RXD */
+	GPIO_NC, /* 17 UART2_RXD */
+	GPIO_NC, /* 18 UART1_CTS_B */
+	GPIO_NC, /* 19 UART2_RTS_B */
+	Native_M2, /* 20 UART1_TXD */
+	GPIO_NC, /* 21 UART2_TXD */
+	GPIO_NC, /* 22 UART2_CTS_B */
+	GPIO_NC, /* 30 MF_HDA_CLK */
+	GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */
+	GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */
+	GPIO_NC, /* 33 MF_HDA_SDO */
+	GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 34 MF_HDA_DOCKRSTB */
+	GPIO_NC, /* 35 MF_HDA_SYNC */
+	GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
+	GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 37 MF_HDA_DOCKENB */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
+	GPIO_NC, /* 46 I2C4_SDA */
+	NATIVE_PU20K(2), /* 47 I2C6_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
+	GPIO_NC, /* 49 I2C_NFC_SDA */
+	GPIO_NC, /* 50 I2C4_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */
+	GPIO_NC, /* 52 I2C_NFC_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */
+	GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/
+	NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 66  I2C2_SCL */
+	GPIO_INPUT_NO_PULL,/* 67  I2C3_SCL,RAMID1 */
+	GPIO_OUT_HIGH, /* 75 SATA_GP0 */
+	GPIO_NC, /* 76 GPI SATA_GP1 */
+	Native_M1, /* 77 SATA_LEDN */
+	GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */
+	Native_M1, /* 79 MF_SMB_ALERTB */
+	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
+	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
+	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
+	Native_M1, /* 90 PCIE_CLKREQ0B */
+	GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
+	Native_M1, /* 92 GP_SSP_2_CLK */
+	NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
+	Native_M1, /* 94 GP_SSP_2_RXD */
+	GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
+	Native_M1, /* 96 GP_SSP_2_FS */
+	NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
+	GPIO_END
+};
+
+
+/* North Community */
+static const struct soc_gpio_map  gpn_gpio_map[] = {
+	Native_M5, /* 00 GPIO_DFX0 */
+	Native_M5, /* 01 GPIO_DFX3 */
+	Native_M1, /* 02 GPIO_DFX7 */
+	Native_M5, /* 03 GPIO_DFX1 */
+	Native_M1, /* 04 GPIO_DFX5 */
+	Native_M1, /* 05 GPIO_DFX4 */
+	GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA),
+	/* 06 GPIO_DFX8 */
+	Native_M5, /* 07 GPIO_DFX2 */
+	Native_M8, /* 08 GPIO_DFX6 */
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
+	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
+	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
+	/* 17 GPIO_SUS3 */
+	GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
+	/* 18 GPIO_SUS7 */
+	GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
+	/* 19 GPIO_SUS1 */
+	GPIO_NC, /* 20 GPIO_SUS5 */
+	GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA),
+	/* 21 SEC_GPIO_SUS11 */
+	GPIO_NC, /* 22 GPIO_SUS4 */
+	GPIO_NC,
+	/* 23 SEC_GPIO_SUS8 */
+	Native_M6, /* 24 GPIO_SUS2 */
+	GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
+	Native_M1, /* 26 CX_PREQ_B */
+	GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */
+	Native_M1, /* 30 TRST_B */
+	Native_M1, /* 31 TCK */
+	GPIO_SKIP, /* 32 PROCHOT_B */
+	GPIO_SKIP, /* 33 SVID0_DATA */
+	Native_M1, /* 34 TMS */
+	GPIO_NC, /* 35 CX_PRDY_B_2 */
+	GPIO_NC, /* 36 TDO_2 */
+	Native_M1, /* 37 CX_PRDY_B */
+	GPIO_SKIP, /* 38 SVID0_ALERT_B */
+	Native_M1, /* 39 TDO */
+	GPIO_SKIP, /* 40 SVID0_CLK */
+	Native_M1, /* 41 TDI */
+	Native_M2, /* 45 GP_CAMERASB05 */
+	Native_M2, /* 46 GP_CAMERASB02 */
+	Native_M2, /* 47 GP_CAMERASB08 */
+	Native_M2, /* 48 GP_CAMERASB00 */
+	Native_M2, /* 49 GP_CAMERASBO6 */
+	GPIO_NC, /* 50 GP_CAMERASB10 */
+	Native_M2, /* 51 GP_CAMERASB03 */
+	GPIO_NC, /* 52 GP_CAMERASB09 */
+	Native_M2, /* 53 GP_CAMERASB01 */
+	Native_M2, /* 54 GP_CAMERASB07 */
+	GPIO_NC, /* 55 GP_CAMERASB11 */
+	Native_M2, /* 56 GP_CAMERASB04 */
+	GPIO_NC, /* 60 PANEL0_BKLTEN */
+	GPIO_NC, /* 61 HV_DDI0_HPD */
+	NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */
+	Native_M1, /* 63 PANEL1_BKLTCTL */
+	NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */
+	GPIO_NC, /* 65 PANEL0_BKLTCTL */
+	GPIO_NC, /* 66 HV_DDI0_DDC_SDA */
+	NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */
+	NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
+	Native_M1, /* 69 PANEL1_VDDEN */
+	Native_M1, /* 70 PANEL1_BKLTEN */
+	GPIO_NC, /* 71 HV_DDI0_DDC_SCL */
+	GPIO_NC, /* 72 PANEL0_VDDEN */
+	GPIO_END
+};
+
+
+/* East Community */
+static const struct soc_gpio_map  gpe_gpio_map[] = {
+	Native_M1, /* 00 PMU_SLP_S3_B */
+	GPIO_NC, /* 01 PMU_BATLOW_B */
+	Native_M1, /* 02 SUS_STAT_B */
+	Native_M1, /* 03 PMU_SLP_S0IX_B */
+	Native_M1, /* 04 PMU_AC_PRESENT */
+	Native_M1, /* 05 PMU_PLTRST_B */
+	Native_M1, /* 06 PMU_SUSCLK */
+	GPIO_NC, /* 07 PMU_SLP_LAN_B */
+	Native_M1, /* 08 PMU_PWRBTN_B */
+	Native_M1, /* 09 PMU_SLP_S4_B */
+	NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
+	GPIO_NC, /* 11 PMU_WAKE_LAN_B */
+	GPIO_NC, /* 15 MF_GPIO_3 */
+	GPIO_NC, /* 16 MF_GPIO_7 */
+	GPIO_NC, /* 17 MF_I2C1_SCL */
+	GPIO_NC, /* 18 MF_GPIO_1 */
+	GPIO_NC, /* 19 MF_GPIO_5 */
+	GPIO_NC, /* 20 MF_GPIO_9 */
+	GPIO_NC, /* 21 MF_GPIO_0 */
+	GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
+	GPIO_NC, /* 23 MF_GPIO_8 */
+	GPIO_NC, /* 24 MF_GPIO_2 */
+	GPIO_NC, /* 25 MF_GPIO_6 */
+	GPIO_NC, /* 26 MF_I2C1_SDA */
+	GPIO_END
+};
+
+
+static struct soc_gpio_config gpio_config = {
+	/* BSW */
+	/* gpio configuration for EVT board which
+	 * is the default configuration for Cyan.
+	 */
+	.north = gpn_gpio_map,
+	.southeast = gpse_gpio_map,
+	.southwest  = gpsw_gpio_map,
+	.east = gpe_gpio_map
+};
+
+struct soc_gpio_config *mainboard_get_gpios(void)
+{
+	return get_override_gpios(&gpio_config);
+}
+
+__attribute__((weak)) struct soc_gpio_config *get_override_gpios(
+		struct soc_gpio_config *config)
+{
+	return config;
+}
diff --git a/src/mainboard/google/cyan/gpio.h b/src/mainboard/google/cyan/gpio.h
new file mode 100644
index 0000000..78f4f0e
--- /dev/null
+++ b/src/mainboard/google/cyan/gpio.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef _BOARD_GPIO_H_
+#define _BOARD_GPIO_H_
+
+struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config);
+#endif
diff --git a/src/mainboard/google/cyan/gpio_pre_evt.c b/src/mainboard/google/cyan/gpio_pre_evt.c
new file mode 100644
index 0000000..415c33e
--- /dev/null
+++ b/src/mainboard/google/cyan/gpio_pre_evt.c
@@ -0,0 +1,271 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright(C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "irqroute.h"
+#include <soc/gpio.h>
+#include <stdlib.h>
+#include <boardid.h>
+#include "onboard.h"
+#include "gpio.h"
+
+
+/* South East Community */
+static const struct soc_gpio_map gpse_gpio_map[] = {
+	Native_M1,/* MF_PLT_CLK0 */
+	GPIO_NC, /* 01 PWM1 */
+	GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
+	GPIO_NC, /* 03 MF_PLT_CLK4 */
+	GPIO_NC, /* 04 MF_PLT_CLK3 */
+	GPIO_NC, /* PWM0 05 */
+	GPIO_NC, /* 06 MF_PLT_CLK5 */
+	GPIO_NC, /* 07 MF_PLT_CLK2 */
+	GPIO_NC, /* 15 SDMMC2_D3_CD_B */
+	Native_M1, /* 16 SDMMC1_CLK */
+	NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
+	GPIO_NC, /* 18 SDMMC2_D1 */
+	GPIO_NC, /* 19 SDMMC2_CLK */
+	NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
+	GPIO_NC, /* 21 SDMMC2_D2 */
+	GPIO_NC, /* 22 SDMMC2_CMD  */
+	NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
+	NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
+	GPIO_NC, /* 25 SDMMC2_D0 */
+	NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
+	NATIVE_PU20K(1), /* 30 SDMMC3_D1 */
+	Native_M1, /* 31 SDMMC3_CLK */
+	NATIVE_PU20K(1), /* 32 SDMMC3_D3 */
+	NATIVE_PU20K(1), /* 33 SDMMC3_D2 */
+	NATIVE_PU20K(1), /* 34 SDMMC3_CMD */
+	NATIVE_PU20K(1), /* 35 SDMMC3_D0 */
+	NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
+	Native_M1, /* 46 LPC_CLKRUNB */
+	NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
+	Native_M1, /* 48 LPC_FRAMEB */
+	Native_M1, /* 49 MF_LPC_CLKOUT1 */
+	NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
+	Native_M1, /* 51 MF_LPC_CLKOUT0 */
+	NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
+	Native_M1,/* SPI1_MISO */
+	Native_M1, /* 61 SPI1_CS0_B */
+	Native_M1, /* SPI1_CLK */
+	NATIVE_PU20K(1), /* 63 MMC1_D6 */
+	Native_M1, /* 62 SPI1_MOSI */
+	NATIVE_PU20K(1), /* 65 MMC1_D5 */
+	GPIO_NC, /* SPI1_CS1_B  66 */
+	NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
+	NATIVE_PU20K(1), /* 68 MMC1_D7 */
+	GPIO_NC, /* 69 MMC1_RCLK */
+	Native_M1, /* 75  GPO USB_OC1_B */
+	Native_M1, /* 76  PMU_RESETBUTTON_B */
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	/* GPIO_ALERT 77   */
+	Native_M1, /* 78  SDMMC3_PWR_EN_B */
+	GPIO_NC, /* 79  GPI ILB_SERIRQ */
+	Native_M1, /* 80  USB_OC0_B */
+	NATIVE_INT(1, L1), /* 81  SDMMC3_CD_B */
+	GPIO_NC,  /* 82  spkr	 asummed gpio number */
+	Native_M1, /* 83 SUSPWRDNACK */
+	SPARE_PIN,/* 84 spare pin */
+	Native_M1, /* 85 SDMMC3_1P8_EN */
+	GPIO_END
+};
+
+/* South West Community */
+static const struct soc_gpio_map  gpsw_gpio_map[] = {
+	GPIO_NC, /* 00 FST_SPI_D2 */
+	Native_M1, /* 01 FST_SPI_D0 */
+	Native_M1, /* 02 FST_SPI_CLK */
+	GPIO_NC, /* 03 FST_SPI_D3 */
+	GPIO_NC, /* GPO FST_SPI_CS1_B */
+	Native_M1, /* 05 FST_SPI_D1 */
+	Native_M1, /* 06 FST_SPI_CS0_B */
+	GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */
+	GPIO_NC, /* 15 UART1_RTS_B */
+	Native_M2, /* 16 UART1_RXD */
+	GPIO_NC, /* 17 UART2_RXD */
+	GPIO_NC, /* 18 UART1_CTS_B */
+	GPIO_NC, /* 19 UART2_RTS_B */
+	Native_M2, /* 20 UART1_TXD */
+	GPIO_NC, /* 21 UART2_TXD */
+	GPIO_NC, /* 22 UART2_CTS_B */
+	GPIO_NC, /* 30 MF_HDA_CLK */
+	GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */
+	GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */
+	GPIO_NC, /* 33 MF_HDA_SDO */
+	GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 34 MF_HDA_DOCKRSTB */
+	GPIO_NC, /* 35 MF_HDA_SYNC */
+	GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
+	GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 37 MF_HDA_DOCKENB */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
+	GPIO_NC, /* 46 I2C4_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
+	GPIO_NC, /* 49 I2C_NFC_SDA */
+	GPIO_NC, /* 50 I2C4_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */
+	GPIO_NC, /* 52 I2C_NFC_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */
+	GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/
+	NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */
+	NATIVE_PU1K_CSEN_INVTX(1), /* 66  I2C2_SCL */
+	GPIO_INPUT_NO_PULL,/* 67  I2C3_SCL,RAMID1 */
+	GPIO_OUT_HIGH, /* 75 SATA_GP0 */
+	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
+	/* 76 GPI SATA_GP1 */
+	Native_M1, /* 77 SATA_LEDN */
+	GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */
+	Native_M1, /* 79 MF_SMB_ALERTB */
+	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
+	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
+	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
+	Native_M1, /* 90 PCIE_CLKREQ0B */
+	GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
+	Native_M1, /* 92 GP_SSP_2_CLK */
+	NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
+	Native_M1, /* 94 GP_SSP_2_RXD */
+	GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
+		/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
+	Native_M1, /* 96 GP_SSP_2_FS */
+	NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
+	GPIO_END
+};
+
+
+/* North Community */
+static const struct soc_gpio_map  gpn_gpio_map[] = {
+	Native_M5, /* 00 GPIO_DFX0 */
+	Native_M5, /* 01 GPIO_DFX3 */
+	Native_M1, /* 02 GPIO_DFX7 */
+	Native_M5, /* 03 GPIO_DFX1 */
+	Native_M1, /* 04 GPIO_DFX5 */
+	Native_M1, /* 05 GPIO_DFX4 */
+	GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA),
+	/* 06 GPIO_DFX8 */
+	Native_M5, /* 07 GPIO_DFX2 */
+	Native_M8, /* 08 GPIO_DFX6 */
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
+	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
+	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
+	/* 17 GPIO_SUS3 */
+	GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
+	/* 18 GPIO_SUS7 */
+	GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */
+	GPIO_NC, /* 20 GPIO_SUS5 */
+	GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA),
+	/* 21 SEC_GPIO_SUS11 */
+	GPIO_NC, /* 22 GPIO_SUS4 */
+	GPIO_NC,
+	/* 23 SEC_GPIO_SUS8 */
+	Native_M6, /* 24 GPIO_SUS2 */
+	GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
+	Native_M1, /* 26 CX_PREQ_B */
+	GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */
+	Native_M1, /* 30 TRST_B */
+	Native_M1, /* 31 TCK */
+	GPIO_SKIP, /* 32 PROCHOT_B */
+	GPIO_SKIP, /* 33 SVID0_DATA */
+	Native_M1, /* 34 TMS */
+	GPIO_NC, /* 35 CX_PRDY_B_2 */
+	GPIO_NC, /* 36 TDO_2 */
+	Native_M1, /* 37 CX_PRDY_B */
+	GPIO_SKIP, /* 38 SVID0_ALERT_B */
+	Native_M1, /* 39 TDO */
+	GPIO_SKIP, /* 40 SVID0_CLK */
+	Native_M1, /* 41 TDI */
+	Native_M2, /* 45 GP_CAMERASB05 */
+	Native_M2, /* 46 GP_CAMERASB02 */
+	Native_M2, /* 47 GP_CAMERASB08 */
+	Native_M2, /* 48 GP_CAMERASB00 */
+	Native_M2, /* 49 GP_CAMERASBO6 */
+	GPIO_NC, /* 50 GP_CAMERASB10 */
+	Native_M2, /* 51 GP_CAMERASB03 */
+	GPIO_NC, /* 52 GP_CAMERASB09 */
+	Native_M2, /* 53 GP_CAMERASB01 */
+	Native_M2, /* 54 GP_CAMERASB07 */
+	GPIO_NC, /* 55 GP_CAMERASB11 */
+	Native_M2, /* 56 GP_CAMERASB04 */
+	GPIO_NC, /* 60 PANEL0_BKLTEN */
+	GPIO_NC, /* 61 HV_DDI0_HPD */
+	NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */
+	Native_M1, /* 63 PANEL1_BKLTCTL */
+	NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */
+	GPIO_NC, /* 65 PANEL0_BKLTCTL */
+	GPIO_NC, /* 66 HV_DDI0_DDC_SDA */
+	NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */
+	NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
+	Native_M1, /* 69 PANEL1_VDDEN */
+	Native_M1, /* 70 PANEL1_BKLTEN */
+	GPIO_NC, /* 71 HV_DDI0_DDC_SCL */
+	GPIO_NC, /* 72 PANEL0_VDDEN */
+	GPIO_END
+};
+
+/* East Community */
+static const struct soc_gpio_map  gpe_gpio_map[] = {
+	Native_M1, /* 00 PMU_SLP_S3_B */
+	GPIO_NC, /* 01 PMU_BATLOW_B */
+	Native_M1, /* 02 SUS_STAT_B */
+	Native_M1, /* 03 PMU_SLP_S0IX_B */
+	Native_M1, /* 04 PMU_AC_PRESENT */
+	Native_M1, /* 05 PMU_PLTRST_B */
+	Native_M1, /* 06 PMU_SUSCLK */
+	GPIO_NC, /* 07 PMU_SLP_LAN_B */
+	Native_M1, /* 08 PMU_PWRBTN_B */
+	Native_M1, /* 09 PMU_SLP_S4_B */
+	NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
+	GPIO_NC, /* 11 PMU_WAKE_LAN_B */
+	GPIO_NC, /* 15 MF_GPIO_3 */
+	GPIO_NC, /* 16 MF_GPIO_7 */
+	GPIO_NC, /* 17 MF_I2C1_SCL */
+	GPIO_NC, /* 18 MF_GPIO_1 */
+	GPIO_NC, /* 19 MF_GPIO_5 */
+	GPIO_NC, /* 20 MF_GPIO_9 */
+	GPIO_NC, /* 21 MF_GPIO_0 */
+	GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
+	GPIO_NC, /* 23 MF_GPIO_8 */
+	GPIO_NC, /* 24 MF_GPIO_2 */
+	GPIO_NC, /* 25 MF_GPIO_6 */
+	GPIO_NC, /* 26 MF_I2C1_SDA */
+	GPIO_END
+};
+
+static struct soc_gpio_config gpio_config = {
+	/* BSW */
+	/* gpio configuration for pre-evt board */
+	.north = gpn_gpio_map,
+	.southeast = gpse_gpio_map,
+	.southwest  = gpsw_gpio_map,
+	.east = gpe_gpio_map
+};
+
+struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config)
+{
+	if (board_id() == BOARD_PRE_EVT)
+		return &gpio_config;
+
+	return config;
+}
diff --git a/src/mainboard/google/cyan/irqroute.c b/src/mainboard/google/cyan/irqroute.c
new file mode 100644
index 0000000..83207d9
--- /dev/null
+++ b/src/mainboard/google/cyan/irqroute.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/google/cyan/irqroute.h b/src/mainboard/google/cyan/irqroute.h
new file mode 100644
index 0000000..5353d42
--- /dev/null
+++ b/src/mainboard/google/cyan/irqroute.h
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,   C, D, E, F), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(MMC_DEV,  D, E, F, G), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,  A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+	PIRQ_PIC(A, DISABLE), \
+	PIRQ_PIC(B, DISABLE), \
+	PIRQ_PIC(C, DISABLE), \
+	PIRQ_PIC(D, DISABLE), \
+	PIRQ_PIC(E, DISABLE), \
+	PIRQ_PIC(F, DISABLE), \
+	PIRQ_PIC(G, DISABLE), \
+	PIRQ_PIC(H, DISABLE)
+
+/* CORE bank DIRQs - up to 16 supported */
+#define TPAD_IRQ_OFFSET		0
+#define TOUCH_IRQ_OFFSET	1
+#define I8042_IRQ_OFFSET	2
+#define ALS_IRQ_OFFSET		3
+/* Corresponding SCORE GPIO pins */
+#define TPAD_IRQ_GPIO		55
+#define TOUCH_IRQ_GPIO		72
+#define I8042_IRQ_GPIO		101
+#define ALS_IRQ_GPIO		70
+
+/* SUS bank DIRQs - up to 16 supported */
+#define CODEC_IRQ_OFFSET	0
+/* Corresponding SUS GPIO pins */
+#define CODEC_IRQ_GPIO		9
diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c
new file mode 100755
index 0000000..b109574
--- /dev/null
+++ b/src/mainboard/google/cyan/mainboard.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <bootstate.h>
+#include <device/device.h>
+#include <soc/gpio.h>
+#include "ec.h"
+
+static void mainboard_init(device_t dev)
+{
+	mainboard_ec_init();
+}
+
+/*
+ * mainboard_enable is executed as first thing after
+ * enumerate_buses().
+ */
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = mainboard_init;
+}
+
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h
new file mode 100755
index 0000000..3539ff4
--- /dev/null
+++ b/src/mainboard/google/cyan/onboard.h
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include "irqroute.h"
+
+/*
+ * Calculation of gpio based irq.
+ * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
+ * Max direct irq (MAX_DIRECT_IRQ) is 114.
+ * Size of gpio banks are
+ * GPSW_SIZE = 98
+ * GPNC_SIZE = 73
+ * GPEC_SIZE = 27
+ * GPSE_SIZE = 86
+ */
+
+/*
+ * gpio based irq for kbd, 17th index in North Bank
+ * MAX_DIRECT_IRQ + GPSW_SIZE + 18
+ */
+/* ToDO: change kbd irq to gpio bank index */
+#define CYAN_KBD_IRQ         182
+
+
+/* SCI: Gpio index in N bank */
+#define CYAN_SCI_GPIO_INDEX		15
+/* Trackpad: Gpio index in N bank */
+#define CYAN_TRACKPAD_GPIO_INDEX	18
+/* Touch: Gpio index in SW bank */
+#define CYAN_TOUCH_GPIO_INDEX		76
+/* EVT Touch: Gpio index in N bank */
+#define CYAN_EVT_TOUCH_GPIO_INDEX	19
+/* TI Audio: Gpio index in SW bank */
+#define CYAN_JACK_TI_GPIO_INDEX		34
+/* MAXIM Audio: Gpio index in SE bank */
+#define CYAN_JACK_MAXIM_GPIO_INDEX	77
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          5
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_TOUCHSCREEN_NAME          "touchscreen"
+#define BOARD_TOUCHSCREEN_WAKE_GPIO     ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS       0
+#define BOARD_TOUCHSCREEN_I2C_ADDR      0x4a    /* TODO(shawnn): Check this */
+
+#define BOARD_I8042_IRQ                 CYAN_KBD_IRQ
+#define BOARD_ALS_IRQ                   GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
+
+/* SD CARD gpio */
+#define SDCARD_CD			81
+
+#define AUDIO_CODEC_HID			"193C9890"
+#define AUDIO_CODEC_CID			"193C9890"
+#define AUDIO_CODEC_DDN			"Maxim 98090 Codec  "
+#define AUDIO_CODEC_I2C_ADDR		0x10
+
+#define TI_SWITCH_HID           "104C227E"
+#define TI_SWITCH_CID           "104C227E"
+#define TI_SWITCH_DDN           "TI SWITCH "
+#define TI_SWITCH_I2C_ADDR		0x3B
+
+#define BOARD_PRE_EVT		0x01
+#define BOARD_EVT		0x02
+#endif
diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c
new file mode 100644
index 0000000..136d189
--- /dev/null
+++ b/src/mainboard/google/cyan/ramstage.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/ramstage.h>
+#include <boardid.h>
+#include "onboard.h"
+
+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+{
+	if (board_id() == BOARD_PRE_EVT)
+		params->ChvSvidConfig = SVID_CONFIG3;
+}
diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c
new file mode 100755
index 0000000..22e26b5
--- /dev/null
+++ b/src/mainboard/google/cyan/romstage.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <lib.h>
+#include <soc/gpio.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+/* All FSP specific code goes in this block */
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+	struct pei_data *ps = rp->pei_data;
+
+	mainboard_fill_spd_data(ps);
+
+	/* Call back into chipset code with platform values updated. */
+	romstage_common(rp);
+}
+
+void mainboard_memory_init_params(struct romstage_params *params,
+	MEMORY_INIT_UPD *memory_params)
+{
+	/* Update SPD data */
+	memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;
+	memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;
+	memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;
+}
diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c
new file mode 100644
index 0000000..5af0421
--- /dev/null
+++ b/src/mainboard/google/cyan/smihandler.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "ec.h"
+#include <ec/google/chromeec/ec.h>
+#include <elog.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+
+/* The wake gpio is SUS_GPIO[0]. */
+#define WAKE_GPIO_EN SUS_GPIO_EN0
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		smm_get_gnvs()->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/*
+	 * On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+static uint8_t mainboard_smi_ec(void)
+{
+	uint8_t cmd = google_chromeec_get_event();
+	uint16_t pmbase = get_pmbase();
+	uint32_t pm1_cnt;
+
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
+	/* Log this event */
+	if (cmd)
+		elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
+#endif
+
+	switch (cmd) {
+	case EC_HOST_EVENT_LID_CLOSED:
+		printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+		/* Go to S5 */
+		pm1_cnt = inl(pmbase + PM1_CNT);
+		pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
+		outl(pm1_cnt, pmbase + PM1_CNT);
+		break;
+	}
+
+	return cmd;
+}
+#endif
+
+/*
+ * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
+ * this includes the enable bits in the lower 16 bits.
+ */
+void mainboard_smi_gpi(uint32_t alt_gpio_smi)
+{
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
+		/* Process all pending events */
+		while (mainboard_smi_ec() != 0)
+			;
+	}
+#endif
+}
+
+void mainboard_smi_sleep(uint8_t slp_typ)
+{
+	/* Disable USB charging if required */
+	switch (slp_typ) {
+	case 3:
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+		if (smm_get_gnvs()->s3u0 == 0)
+			google_chromeec_set_usb_charge_mode(
+				0, USB_CHARGE_MODE_DISABLED);
+		if (smm_get_gnvs()->s3u1 == 0)
+			google_chromeec_set_usb_charge_mode(
+				1, USB_CHARGE_MODE_DISABLED);
+
+		/* Enable wake events */
+		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+#endif
+		/* Enable wake pin in GPE block. */
+		enable_gpe(WAKE_GPIO_EN);
+		break;
+	case 5:
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+		if (smm_get_gnvs()->s5u0 == 0)
+			google_chromeec_set_usb_charge_mode(
+				0, USB_CHARGE_MODE_DISABLED);
+		if (smm_get_gnvs()->s5u1 == 0)
+			google_chromeec_set_usb_charge_mode(
+				1, USB_CHARGE_MODE_DISABLED);
+
+		/* Enable wake events */
+		google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
+#endif
+		break;
+	}
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	/* Disable SCI and SMI events */
+	google_chromeec_set_smi_mask(0);
+	google_chromeec_set_sci_mask(0);
+
+	/* Clear pending events that may trigger immediate wake */
+	while (google_chromeec_get_event() != 0)
+		;
+#endif
+}
+
+int mainboard_smi_apmc(uint8_t apmc)
+{
+	switch (apmc) {
+	case APM_CNT_ACPI_ENABLE:
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+		google_chromeec_set_smi_mask(0);
+		/* Clear all pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+#endif
+		break;
+	case APM_CNT_ACPI_DISABLE:
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+		google_chromeec_set_sci_mask(0);
+		/* Clear all pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+		google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+#endif
+		break;
+	}
+	return 0;
+}
diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc
new file mode 100644
index 0000000..a861e2c
--- /dev/null
+++ b/src/mainboard/google/cyan/spd/Makefile.inc
@@ -0,0 +1,42 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES =  samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
new file mode 100644
index 0000000..ff4fd29
--- /dev/null
+++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 04 19 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 ff ab
+48 4d 54 34 32 35 53 36
+41 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
new file mode 100644
index 0000000..fdd1a43
--- /dev/null
+++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
@@ -0,0 +1,32 @@
+92 13 0B 03 04 19 02 02
+03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81
+20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01
+00 00 00 00 00 00 C9 C0
+48 4D 54 34 32 35 53 36
+43 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
new file mode 100644
index 0000000..e0b0ac5
--- /dev/null
+++ b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
@@ -0,0 +1,32 @@
+92 12 0B 03 04 19 02 02
+03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81
+20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00
+88 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01
+00 00 00 00 00 00 6C F9
+4D 34 37 31 42 35 36 37
+34 51 48 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
new file mode 100644
index 0000000..0ddf5ee
--- /dev/null
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -0,0 +1,192 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <lib.h>
+#include <memory_info.h>
+#include <smbios.h>
+#include <spd.h>
+#include <soc/gpio.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+#define SPD_SIZE		256
+#define SATA_GP3_PAD_CFG0       0x5828
+#define I2C3_SCL_PAD_CFG0       0x5438
+#define MF_PLT_CLK1_PAD_CFG0    0x4410
+#define I2C3_SDA_PAD_CFG0       0x5420
+
+/*
+ * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b0001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b0011 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ */
+static const uint32_t dual_channel_config = (1 << 0) | (1 << 1);
+
+static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
+{
+	int ram_id = 0;
+	ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0;
+	ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1;
+	ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0)
+		<< 2;
+	ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3;
+	printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
+	if (ram_id >= total_spds)
+		return NULL;
+
+	/* Determine if this is a single or dual channel memory system */
+	if (dual_channel_config & (1 << ram_id))
+		*dual = 1;
+
+	/* Display the RAM type */
+	switch (ram_id) {
+	case 0:
+	case 2:
+		printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n");
+		break;
+	case 1:
+	case 3:
+		printk(BIOS_DEBUG, "2GiB Hynix  H5TC4G63CFR-PBA 1600MHz\n");
+		break;
+	}
+
+	/* Return the serial product data for the RAM */
+	return &spd_file_content[SPD_SIZE * ram_id];
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *ps)
+{
+	char *spd_file;
+	size_t spd_file_len;
+	void *spd_content;
+	int dual_channel = 0;
+
+	/* Find the SPD data in CBFS. */
+	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+		&spd_file_len);
+	if (!spd_file)
+		die("SPD data not found.");
+
+	if (spd_file_len < SPD_SIZE)
+		die("Missing SPD data.");
+
+	/*
+	 * Both channels are always present in SPD data. Always use matched
+	 * DIMMs so use the same SPD data for each DIMM.
+	 */
+	spd_content = get_spd_pointer(spd_file,
+				      spd_file_len / SPD_SIZE,
+				      &dual_channel);
+	if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) {
+		printk(BIOS_DEBUG, "SPD Data:\n");
+		hexdump(spd_content, SPD_SIZE);
+		printk(BIOS_DEBUG, "\n");
+	}
+
+	/*
+	 * Set SPD and memory configuration:
+	 * Memory type: 0=DimmInstalled,
+	 *              1=SolderDownMemory,
+	 *              2=DimmDisabled
+	 */
+	if (spd_content != NULL) {
+		ps->spd_data_ch0 = spd_content;
+		ps->spd_ch0_config = 1;
+		printk(BIOS_DEBUG, "Channel 0 DIMM soldered down\n");
+		if (dual_channel) {
+			printk(BIOS_DEBUG, "Channel 1 DIMM soldered down\n");
+			ps->spd_data_ch1 = spd_content;
+			ps->spd_ch1_config = 1;
+		} else {
+			printk(BIOS_DEBUG, "Channel 1 DIMM not installed\n");
+			ps->spd_ch1_config = 2;
+		}
+	}
+}
+
+static void set_dimm_info(uint32_t chips, uint8_t *spd, struct dimm_info *dimm)
+{
+	uint16_t clock_frequency;
+	uint32_t log2_chips;
+
+	/* Parse the SPD data to determine the DIMM information */
+	dimm->ddr_type = MEMORY_TYPE_DDR3;
+	dimm->dimm_size = (chips << (spd[4] & 0xf)) << (28 - 3 - 20);  /* MiB */
+	clock_frequency = 1000 * spd[11] / (spd[10] * spd[12]);	/* MHz */
+	dimm->ddr_frequency = 2 * clock_frequency;	/* Double Data Rate */
+	dimm->mod_type = spd[3] & 0xf;
+	memcpy((char *)&dimm->module_part_number[0], &spd[0x80],
+		sizeof(dimm->module_part_number) - 1);
+	dimm->mod_id = *(uint16_t *)&spd[0x94];
+	switch (chips) {
+	case 1:
+		log2_chips = 0;
+		break;
+
+	case 2:
+		log2_chips = 1;
+		break;
+
+	case 4:
+		log2_chips = 2;
+		break;
+
+	case 8:
+		log2_chips = 3;
+		break;
+	}
+	dimm->bus_width = (uint8_t)(log2_chips + (spd[7] & 7) + 2 - 3);
+}
+
+void mainboard_save_dimm_info(struct romstage_params *params)
+{
+	struct dimm_info *dimm;
+	struct memory_info *mem_info;
+	uint32_t chips;
+
+	/*
+	 * Allocate CBMEM area for DIMM information used to populate SMBIOS
+	 * table 17
+	 */
+	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+	printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
+	if (mem_info == NULL)
+		return;
+	memset(mem_info, 0, sizeof(*mem_info));
+
+	/* Describe the first channel memory */
+	chips = 4;
+	dimm = &mem_info->dimm[0];
+	set_dimm_info(chips, params->pei_data->spd_data_ch0, dimm);
+	mem_info->dimm_cnt = 1;
+
+	/* Describe the second channel memory */
+	if (params->pei_data->spd_ch1_config == 1) {
+		dimm = &mem_info->dimm[1];
+		set_dimm_info(chips, params->pei_data->spd_data_ch1, dimm);
+		dimm->channel_num = 1;
+		mem_info->dimm_cnt = 2;
+	}
+}
diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c
new file mode 100644
index 0000000..4399d88
--- /dev/null
+++ b/src/mainboard/google/cyan/w25q64.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/spi.h>
+#include <string.h>
+
+/*
+ * SPI lockdown configuration W25Q64FW.
+ */
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
+		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
+		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
+
+static const struct spi_config spi_config = {
+	.preop = SPI_OPPREFIX,
+	.optype = SPI_OPTYPE,
+	.opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+	.lvscc =  SPI_VSCC,
+	.uvscc =  SPI_VSCC,
+};
+
+int mainboard_get_spi_config(struct spi_config *cfg)
+{
+	memcpy(cfg, &spi_config, sizeof(*cfg));
+
+	return 0;
+}



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